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Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/hal_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c269
1 files changed, 269 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
new file mode 100644
index 00000000..a656f10d
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -0,0 +1,269 @@
1/*
2 * GP10B Tegra HAL interface
3 *
4 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/types.h>
17#include <linux/printk.h>
18#include <linux/version.h>
19
20#include <linux/types.h>
21
22#include "gk20a/gk20a.h"
23
24#include "gp10b/gr_gp10b.h"
25#include "gp10b/fecs_trace_gp10b.h"
26#include "gp10b/mc_gp10b.h"
27#include "gp10b/ltc_gp10b.h"
28#include "gp10b/mm_gp10b.h"
29#include "gp10b/ce_gp10b.h"
30#include "gp10b/fb_gp10b.h"
31#include "gp10b/pmu_gp10b.h"
32#include "gp10b/gr_ctx_gp10b.h"
33#include "gp10b/fifo_gp10b.h"
34#include "gp10b/gp10b_gating_reglist.h"
35#include "gp10b/regops_gp10b.h"
36#include "gp10b/cde_gp10b.h"
37#include "gp10b/therm_gp10b.h"
38
39#include "gm20b/gr_gm20b.h"
40#include "gm20b/fifo_gm20b.h"
41#include "gm20b/pmu_gm20b.h"
42#include "gm20b/clk_gm20b.h"
43#include <linux/tegra-fuse.h>
44
45#include "gp10b.h"
46#include "hw_proj_gp10b.h"
47#include "gk20a/dbg_gpu_gk20a.h"
48#include "gk20a/css_gr_gk20a.h"
49
50#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)
51#define FUSE_OPT_PRIV_SEC_EN_0 0x264
52#endif
53#define PRIV_SECURITY_ENABLED 0x01
54
55static struct gpu_ops gp10b_ops = {
56 .clock_gating = {
57 .slcg_bus_load_gating_prod =
58 gp10b_slcg_bus_load_gating_prod,
59 .slcg_ce2_load_gating_prod =
60 gp10b_slcg_ce2_load_gating_prod,
61 .slcg_chiplet_load_gating_prod =
62 gp10b_slcg_chiplet_load_gating_prod,
63 .slcg_ctxsw_firmware_load_gating_prod =
64 gp10b_slcg_ctxsw_firmware_load_gating_prod,
65 .slcg_fb_load_gating_prod =
66 gp10b_slcg_fb_load_gating_prod,
67 .slcg_fifo_load_gating_prod =
68 gp10b_slcg_fifo_load_gating_prod,
69 .slcg_gr_load_gating_prod =
70 gr_gp10b_slcg_gr_load_gating_prod,
71 .slcg_ltc_load_gating_prod =
72 ltc_gp10b_slcg_ltc_load_gating_prod,
73 .slcg_perf_load_gating_prod =
74 gp10b_slcg_perf_load_gating_prod,
75 .slcg_priring_load_gating_prod =
76 gp10b_slcg_priring_load_gating_prod,
77 .slcg_pmu_load_gating_prod =
78 gp10b_slcg_pmu_load_gating_prod,
79 .slcg_therm_load_gating_prod =
80 gp10b_slcg_therm_load_gating_prod,
81 .slcg_xbar_load_gating_prod =
82 gp10b_slcg_xbar_load_gating_prod,
83 .blcg_bus_load_gating_prod =
84 gp10b_blcg_bus_load_gating_prod,
85 .blcg_ce_load_gating_prod =
86 gp10b_blcg_ce_load_gating_prod,
87 .blcg_ctxsw_firmware_load_gating_prod =
88 gp10b_blcg_ctxsw_firmware_load_gating_prod,
89 .blcg_fb_load_gating_prod =
90 gp10b_blcg_fb_load_gating_prod,
91 .blcg_fifo_load_gating_prod =
92 gp10b_blcg_fifo_load_gating_prod,
93 .blcg_gr_load_gating_prod =
94 gp10b_blcg_gr_load_gating_prod,
95 .blcg_ltc_load_gating_prod =
96 gp10b_blcg_ltc_load_gating_prod,
97 .blcg_pwr_csb_load_gating_prod =
98 gp10b_blcg_pwr_csb_load_gating_prod,
99 .blcg_pmu_load_gating_prod =
100 gp10b_blcg_pmu_load_gating_prod,
101 .blcg_xbar_load_gating_prod =
102 gp10b_blcg_xbar_load_gating_prod,
103 .pg_gr_load_gating_prod =
104 gr_gp10b_pg_gr_load_gating_prod,
105 }
106};
107
108static int gp10b_get_litter_value(struct gk20a *g, int value)
109{
110 int ret = EINVAL;
111 switch (value) {
112 case GPU_LIT_NUM_GPCS:
113 ret = proj_scal_litter_num_gpcs_v();
114 break;
115 case GPU_LIT_NUM_PES_PER_GPC:
116 ret = proj_scal_litter_num_pes_per_gpc_v();
117 break;
118 case GPU_LIT_NUM_ZCULL_BANKS:
119 ret = proj_scal_litter_num_zcull_banks_v();
120 break;
121 case GPU_LIT_NUM_TPC_PER_GPC:
122 ret = proj_scal_litter_num_tpc_per_gpc_v();
123 break;
124 case GPU_LIT_NUM_FBPS:
125 ret = proj_scal_litter_num_fbps_v();
126 break;
127 case GPU_LIT_GPC_BASE:
128 ret = proj_gpc_base_v();
129 break;
130 case GPU_LIT_GPC_STRIDE:
131 ret = proj_gpc_stride_v();
132 break;
133 case GPU_LIT_GPC_SHARED_BASE:
134 ret = proj_gpc_shared_base_v();
135 break;
136 case GPU_LIT_TPC_IN_GPC_BASE:
137 ret = proj_tpc_in_gpc_base_v();
138 break;
139 case GPU_LIT_TPC_IN_GPC_STRIDE:
140 ret = proj_tpc_in_gpc_stride_v();
141 break;
142 case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
143 ret = proj_tpc_in_gpc_shared_base_v();
144 break;
145 case GPU_LIT_PPC_IN_GPC_BASE:
146 ret = proj_ppc_in_gpc_base_v();
147 break;
148 case GPU_LIT_PPC_IN_GPC_STRIDE:
149 ret = proj_ppc_in_gpc_stride_v();
150 break;
151 case GPU_LIT_PPC_IN_GPC_SHARED_BASE:
152 ret = proj_ppc_in_gpc_shared_base_v();
153 break;
154 case GPU_LIT_ROP_BASE:
155 ret = proj_rop_base_v();
156 break;
157 case GPU_LIT_ROP_STRIDE:
158 ret = proj_rop_stride_v();
159 break;
160 case GPU_LIT_ROP_SHARED_BASE:
161 ret = proj_rop_shared_base_v();
162 break;
163 case GPU_LIT_HOST_NUM_ENGINES:
164 ret = proj_host_num_engines_v();
165 break;
166 case GPU_LIT_HOST_NUM_PBDMA:
167 ret = proj_host_num_pbdma_v();
168 break;
169 case GPU_LIT_LTC_STRIDE:
170 ret = proj_ltc_stride_v();
171 break;
172 case GPU_LIT_LTS_STRIDE:
173 ret = proj_lts_stride_v();
174 break;
175 /* GP10B does not have a FBPA unit, despite what's listed in the
176 * hw headers or read back through NV_PTOP_SCAL_NUM_FBPAS,
177 * so hardcode all values to 0.
178 */
179 case GPU_LIT_NUM_FBPAS:
180 case GPU_LIT_FBPA_STRIDE:
181 case GPU_LIT_FBPA_BASE:
182 case GPU_LIT_FBPA_SHARED_BASE:
183 ret = 0;
184 break;
185 default:
186 gk20a_err(dev_from_gk20a(g), "Missing definition %d", value);
187 BUG();
188 break;
189 }
190
191 return ret;
192}
193
194int gp10b_init_hal(struct gk20a *g)
195{
196 struct gpu_ops *gops = &g->ops;
197 struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
198 struct gk20a_platform *platform = dev_get_drvdata(g->dev);
199 u32 val;
200
201 *gops = gp10b_ops;
202 gops->pmupstate = false;
203#ifdef CONFIG_TEGRA_ACR
204 if (platform->is_fmodel) {
205 gops->privsecurity = 0;
206 gops->securegpccs = 0;
207 } else {
208 tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0, &val);
209 if (val & PRIV_SECURITY_ENABLED) {
210 gops->privsecurity = 1;
211 gops->securegpccs =1;
212 } else {
213 gk20a_dbg_info("priv security is disabled in HW");
214 gops->privsecurity = 0;
215 gops->securegpccs = 0;
216 }
217 }
218#else
219 if (platform->is_fmodel) {
220 gk20a_dbg_info("running simulator with PRIV security disabled");
221 gops->privsecurity = 0;
222 gops->securegpccs = 0;
223 } else {
224 tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0, &val);
225 if (val & PRIV_SECURITY_ENABLED) {
226 gk20a_dbg_info("priv security is not supported but enabled");
227 gops->privsecurity = 1;
228 gops->securegpccs =1;
229 return -EPERM;
230 } else {
231 gops->privsecurity = 0;
232 gops->securegpccs = 0;
233 }
234 }
235#endif
236
237 gp10b_init_mc(gops);
238 gp10b_init_gr(gops);
239 gp10b_init_fecs_trace_ops(gops);
240 gp10b_init_ltc(gops);
241 gp10b_init_fb(gops);
242 gp10b_init_fifo(gops);
243 gp10b_init_ce(gops);
244 gp10b_init_gr_ctx(gops);
245 gp10b_init_mm(gops);
246 gp10b_init_pmu_ops(gops);
247 gk20a_init_debug_ops(gops);
248 gk20a_init_dbg_session_ops(gops);
249 gp10b_init_regops(gops);
250 gp10b_init_cde_ops(gops);
251 gp10b_init_therm_ops(gops);
252 gk20a_init_tsg_ops(gops);
253#if defined(CONFIG_GK20A_CYCLE_STATS)
254 gk20a_init_css_ops(gops);
255#endif
256 gops->name = "gp10b";
257 gops->chip_init_gpu_characteristics = gp10b_init_gpu_characteristics;
258 gops->get_litter_value = gp10b_get_litter_value;
259 gops->read_ptimer = gk20a_read_ptimer;
260
261 c->twod_class = FERMI_TWOD_A;
262 c->threed_class = PASCAL_A;
263 c->compute_class = PASCAL_COMPUTE_A;
264 c->gpfifo_class = PASCAL_CHANNEL_GPFIFO_A;
265 c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B;
266 c->dma_copy_class = PASCAL_DMA_COPY_A;
267
268 return 0;
269}
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-26 07:51:30 -0400