summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/gr_gp10b.h')
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
index 3b0f0f2e..1d39a38b 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * GP10B GPU GR 2 * GP10B GPU GR
3 * 3 *
4 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -77,6 +77,8 @@ int gr_gp10b_commit_global_cb_manager(struct gk20a *g,
77void gr_gp10b_commit_global_pagepool(struct gk20a *g, 77void gr_gp10b_commit_global_pagepool(struct gk20a *g,
78 struct channel_ctx_gk20a *ch_ctx, 78 struct channel_ctx_gk20a *ch_ctx,
79 u64 addr, u32 size, bool patch); 79 u64 addr, u32 size, bool patch);
80u32 gr_gp10b_get_gpcs_swdx_dss_zbc_c_format_reg(struct gk20a *g);
81u32 gr_gp10b_get_gpcs_swdx_dss_zbc_z_format_reg(struct gk20a *g);
80int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, 82int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr,
81 struct zbc_entry *color_val, u32 index); 83 struct zbc_entry *color_val, u32 index);
82int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, 84int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr,