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-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.h171
1 files changed, 171 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
new file mode 100644
index 00000000..45ac5305
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
@@ -0,0 +1,171 @@
1/*
2 * GP10B GPU GR
3 *
4 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _NVGPU_GR_GP10B_H_
26#define _NVGPU_GR_GP10B_H_
27
28#include "gk20a/mm_gk20a.h"
29
30struct gk20a;
31struct gr_gk20a_isr_data;
32struct channel_ctx_gk20a;
33struct zbc_entry;
34struct gr_ctx_desc;
35struct nvgpu_preemption_modes_rec;
36struct gk20a_debug_output;
37
38enum {
39 PASCAL_CHANNEL_GPFIFO_A = 0xC06F,
40 PASCAL_A = 0xC097,
41 PASCAL_COMPUTE_A = 0xC0C0,
42 PASCAL_DMA_COPY_A = 0xC0B5,
43 PASCAL_DMA_COPY_B = 0xC1B5,
44};
45
46#define NVC097_SET_GO_IDLE_TIMEOUT 0x022c
47#define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc
48#define NVC097_SET_COALESCE_BUFFER_SIZE 0x1028
49#define NVC097_SET_RD_COALESCE 0x102c
50#define NVC097_SET_CIRCULAR_BUFFER_SIZE 0x1280
51#define NVC097_SET_SHADER_EXCEPTIONS 0x1528
52#define NVC097_SET_BES_CROP_DEBUG3 0x10c4
53#define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528
54#define NVC0C0_SET_RD_COALESCE 0x0228
55
56int gr_gp10b_init_fs_state(struct gk20a *g);
57int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size,
58 struct nvgpu_mem *mem);
59void gr_gp10b_create_sysfs(struct gk20a *g);
60int gr_gp10b_handle_fecs_error(struct gk20a *g,
61 struct channel_gk20a *__ch,
62 struct gr_gk20a_isr_data *isr_data);
63int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g,
64 struct channel_gk20a *fault_ch);
65
66bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num);
67bool gr_gp10b_is_valid_gfx_class(struct gk20a *g, u32 class_num);
68bool gr_gp10b_is_valid_compute_class(struct gk20a *g, u32 class_num);
69int gr_gp10b_handle_sm_exception(struct gk20a *g,
70 u32 gpc, u32 tpc, u32 sm,
71 bool *post_event, struct channel_gk20a *fault_ch,
72 u32 *hww_global_esr);
73int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
74 bool *post_event);
75int gr_gp10b_commit_global_cb_manager(struct gk20a *g,
76 struct channel_gk20a *c, bool patch);
77void gr_gp10b_commit_global_pagepool(struct gk20a *g,
78 struct channel_ctx_gk20a *ch_ctx,
79 u64 addr, u32 size, bool patch);
80int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr,
81 struct zbc_entry *color_val, u32 index);
82int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr,
83 struct zbc_entry *depth_val, u32 index);
84u32 gr_gp10b_pagepool_default_size(struct gk20a *g);
85int gr_gp10b_calc_global_ctx_buffer_size(struct gk20a *g);
86void gr_gp10b_set_bes_crop_debug3(struct gk20a *g, u32 data);
87int gr_gp10b_handle_sw_method(struct gk20a *g, u32 addr,
88 u32 class_num, u32 offset, u32 data);
89void gr_gp10b_cb_size_default(struct gk20a *g);
90void gr_gp10b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data);
91void gr_gp10b_set_circular_buffer_size(struct gk20a *g, u32 data);
92int gr_gp10b_init_ctx_state(struct gk20a *g);
93int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
94 struct gr_ctx_desc *gr_ctx,
95 struct vm_gk20a *vm, u32 class,
96 u32 graphics_preempt_mode,
97 u32 compute_preempt_mode);
98int gr_gp10b_alloc_gr_ctx(struct gk20a *g,
99 struct gr_ctx_desc **gr_ctx, struct vm_gk20a *vm,
100 u32 class,
101 u32 flags);
102void gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
103 struct gr_ctx_desc *gr_ctx);
104void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g,
105 struct channel_ctx_gk20a *ch_ctx,
106 struct nvgpu_mem *mem);
107int gr_gp10b_dump_gr_status_regs(struct gk20a *g,
108 struct gk20a_debug_output *o);
109int gr_gp10b_wait_empty(struct gk20a *g, unsigned long duration_ms,
110 u32 expect_delay);
111void gr_gp10b_commit_global_attrib_cb(struct gk20a *g,
112 struct channel_ctx_gk20a *ch_ctx,
113 u64 addr, bool patch);
114void gr_gp10b_commit_global_bundle_cb(struct gk20a *g,
115 struct channel_ctx_gk20a *ch_ctx,
116 u64 addr, u64 size, bool patch);
117int gr_gp10b_load_smid_config(struct gk20a *g);
118void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index);
119void gr_gp10b_get_access_map(struct gk20a *g,
120 u32 **whitelist, int *num_entries);
121int gr_gp10b_pre_process_sm_exception(struct gk20a *g,
122 u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr,
123 bool sm_debugger_attached, struct channel_gk20a *fault_ch,
124 bool *early_exit, bool *ignore_debugger);
125u32 gp10b_gr_get_sm_hww_warp_esr(struct gk20a *g,
126 u32 gpc, u32 tpc, u32 sm);
127u32 get_ecc_override_val(struct gk20a *g);
128int gr_gp10b_suspend_contexts(struct gk20a *g,
129 struct dbg_session_gk20a *dbg_s,
130 int *ctx_resident_ch_fd);
131int gr_gp10b_set_boosted_ctx(struct channel_gk20a *ch,
132 bool boost);
133void gr_gp10b_update_boosted_ctx(struct gk20a *g, struct nvgpu_mem *mem,
134 struct gr_ctx_desc *gr_ctx);
135int gr_gp10b_set_preemption_mode(struct channel_gk20a *ch,
136 u32 graphics_preempt_mode,
137 u32 compute_preempt_mode);
138int gr_gp10b_get_preemption_mode_flags(struct gk20a *g,
139 struct nvgpu_preemption_modes_rec *preemption_modes_rec);
140int gp10b_gr_fuse_override(struct gk20a *g);
141int gr_gp10b_init_preemption_state(struct gk20a *g);
142void gr_gp10b_set_preemption_buffer_va(struct gk20a *g,
143 struct nvgpu_mem *mem, u64 gpu_va);
144int gr_gp10b_set_czf_bypass(struct gk20a *g, struct channel_gk20a *ch);
145void gr_gp10b_init_czf_bypass(struct gk20a *g);
146void gr_gp10b_init_ctxsw_hdr_data(struct gk20a *g, struct nvgpu_mem *mem);
147
148struct gr_t18x {
149 struct {
150 u32 preempt_image_size;
151 bool force_preemption_gfxp;
152 bool force_preemption_cilp;
153 bool dump_ctxsw_stats_on_channel_close;
154 } ctx_vars;
155
156 u32 fecs_feature_override_ecc_val;
157
158 int cilp_preempt_pending_chid;
159};
160
161struct gr_ctx_desc_t18x {
162 struct nvgpu_mem preempt_ctxsw_buffer;
163 struct nvgpu_mem spill_ctxsw_buffer;
164 struct nvgpu_mem betacb_ctxsw_buffer;
165 struct nvgpu_mem pagepool_ctxsw_buffer;
166 u32 ctx_id;
167 bool ctx_id_valid;
168 bool cilp_preempt_pending;
169};
170
171#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-22 16:13:35 -0400