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path: root/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/gr_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index e3ea4603..64ec5e1a 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -1958,8 +1958,13 @@ clean_up:
1958 return gk20a_gr_handle_fecs_error(g, __ch, isr_data); 1958 return gk20a_gr_handle_fecs_error(g, __ch, isr_data);
1959} 1959}
1960 1960
1961static u32 gp10b_mask_hww_warp_esr(u32 hww_warp_esr) 1961static u32 gp10b_gr_get_sm_hww_warp_esr(struct gk20a *g,
1962 u32 gpc, u32 tpc, u32 sm)
1962{ 1963{
1964 u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc);
1965 u32 hww_warp_esr = gk20a_readl(g,
1966 gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset);
1967
1963 if (!(hww_warp_esr & gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m())) 1968 if (!(hww_warp_esr & gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m()))
1964 hww_warp_esr = set_field(hww_warp_esr, 1969 hww_warp_esr = set_field(hww_warp_esr,
1965 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(), 1970 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(),
@@ -2369,7 +2374,6 @@ void gp10b_init_gr(struct gpu_ops *gops)
2369 gops->gr.get_access_map = gr_gp10b_get_access_map; 2374 gops->gr.get_access_map = gr_gp10b_get_access_map;
2370 gops->gr.handle_sm_exception = gr_gp10b_handle_sm_exception; 2375 gops->gr.handle_sm_exception = gr_gp10b_handle_sm_exception;
2371 gops->gr.handle_tex_exception = gr_gp10b_handle_tex_exception; 2376 gops->gr.handle_tex_exception = gr_gp10b_handle_tex_exception;
2372 gops->gr.mask_hww_warp_esr = gp10b_mask_hww_warp_esr;
2373 gops->gr.pre_process_sm_exception = 2377 gops->gr.pre_process_sm_exception =
2374 gr_gp10b_pre_process_sm_exception; 2378 gr_gp10b_pre_process_sm_exception;
2375 gops->gr.handle_fecs_error = gr_gp10b_handle_fecs_error; 2379 gops->gr.handle_fecs_error = gr_gp10b_handle_fecs_error;
@@ -2384,4 +2388,5 @@ void gp10b_init_gr(struct gpu_ops *gops)
2384 gops->gr.set_boosted_ctx = gr_gp10b_set_boosted_ctx; 2388 gops->gr.set_boosted_ctx = gr_gp10b_set_boosted_ctx;
2385 gops->gr.update_boosted_ctx = gr_gp10b_update_boosted_ctx; 2389 gops->gr.update_boosted_ctx = gr_gp10b_update_boosted_ctx;
2386 gops->gr.set_czf_bypass = gr_gp10b_set_czf_bypass; 2390 gops->gr.set_czf_bypass = gr_gp10b_set_czf_bypass;
2391 gops->gr.get_sm_hww_warp_esr = gp10b_gr_get_sm_hww_warp_esr;
2387} 2392}