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Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/gr_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index a43252de..1853aaec 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -27,6 +27,7 @@
27#include "gk20a/gk20a.h" 27#include "gk20a/gk20a.h"
28#include "gk20a/gr_gk20a.h" 28#include "gk20a/gr_gk20a.h"
29#include "gk20a/dbg_gpu_gk20a.h" 29#include "gk20a/dbg_gpu_gk20a.h"
30#include "gk20a/regops_gk20a.h"
30 31
31#include "gm20b/gr_gm20b.h" 32#include "gm20b/gr_gm20b.h"
32#include "gp10b/gr_gp10b.h" 33#include "gp10b/gr_gp10b.h"
@@ -2304,6 +2305,22 @@ static void gr_gp10b_write_preemption_ptr(struct gk20a *g,
2304 2305
2305} 2306}
2306 2307
2308int gr_gp10b_set_czf_bypass(struct gk20a *g, struct channel_gk20a *ch)
2309{
2310 struct nvgpu_dbg_gpu_reg_op ops;
2311
2312 ops.op = REGOP(WRITE_32);
2313 ops.type = REGOP(TYPE_GR_CTX);
2314 ops.status = REGOP(STATUS_SUCCESS);
2315 ops.value_hi = 0;
2316 ops.and_n_mask_lo = gr_gpc0_prop_debug1_czf_bypass_m();
2317 ops.and_n_mask_hi = 0;
2318 ops.offset = gr_gpc0_prop_debug1_r();
2319 ops.value_lo = gr_gpc0_prop_debug1_czf_bypass_f(
2320 g->gr.czf_bypass);
2321
2322 return __gr_gk20a_exec_ctx_ops(ch, &ops, 1, 1, 0, false);
2323}
2307 2324
2308void gp10b_init_gr(struct gpu_ops *gops) 2325void gp10b_init_gr(struct gpu_ops *gops)
2309{ 2326{
@@ -2355,4 +2372,5 @@ void gp10b_init_gr(struct gpu_ops *gops)
2355 gops->gr.load_smid_config = gr_gp10b_load_smid_config; 2372 gops->gr.load_smid_config = gr_gp10b_load_smid_config;
2356 gops->gr.set_boosted_ctx = gr_gp10b_set_boosted_ctx; 2373 gops->gr.set_boosted_ctx = gr_gp10b_set_boosted_ctx;
2357 gops->gr.update_boosted_ctx = gr_gp10b_update_boosted_ctx; 2374 gops->gr.update_boosted_ctx = gr_gp10b_update_boosted_ctx;
2375 gops->gr.set_czf_bypass = gr_gp10b_set_czf_bypass;
2358} 2376}