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Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c741
1 files changed, 741 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c
new file mode 100644
index 00000000..456f3fa0
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c
@@ -0,0 +1,741 @@
1/*
2 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 *
22 * This file is autogenerated. Do not edit.
23 */
24
25#ifndef __gp10b_gating_reglist_h__
26#define __gp10b_gating_reglist_h__
27
28#include "gp10b_gating_reglist.h"
29#include <nvgpu/enabled.h>
30
31struct gating_desc {
32 u32 addr;
33 u32 prod;
34 u32 disable;
35};
36/* slcg bus */
37static const struct gating_desc gp10b_slcg_bus[] = {
38 {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe},
39};
40
41/* slcg ce2 */
42static const struct gating_desc gp10b_slcg_ce2[] = {
43 {.addr = 0x00104204, .prod = 0x00000000, .disable = 0x000007fe},
44};
45
46/* slcg chiplet */
47static const struct gating_desc gp10b_slcg_chiplet[] = {
48 {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007},
49 {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007},
50 {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007},
51 {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007},
52};
53
54/* slcg fb */
55static const struct gating_desc gp10b_slcg_fb[] = {
56 {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe},
57 {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe},
58};
59
60/* slcg fifo */
61static const struct gating_desc gp10b_slcg_fifo[] = {
62 {.addr = 0x000026ac, .prod = 0x00000f40, .disable = 0x0001fffe},
63};
64
65/* slcg gr */
66static const struct gating_desc gp10b_slcg_gr[] = {
67 {.addr = 0x004041f4, .prod = 0x00000002, .disable = 0x03fffffe},
68 {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe},
69 {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x03fffffe},
70 {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe},
71 {.addr = 0x00406004, .prod = 0x00000200, .disable = 0x0001fffe},
72 {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe},
73 {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe},
74 {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe},
75 {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe},
76 {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe},
77 {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x03fffffe},
78 {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe},
79 {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe},
80 {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e},
81 {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x0000003e},
82 {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001},
83 {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe},
84 {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe},
85 {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe},
86 {.addr = 0x00418c74, .prod = 0xffffffc0, .disable = 0xfffffffe},
87 {.addr = 0x00418cf4, .prod = 0xfffffffc, .disable = 0xfffffffe},
88 {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe},
89 {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe},
90 {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe},
91 {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe},
92 {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe},
93 {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x0000ffff},
94 {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e},
95 {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe},
96 {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e},
97 {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e},
98 {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe},
99 {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e},
100 {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e},
101 {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e},
102 {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e},
103 {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe},
104 {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe},
105 {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe},
106 {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e},
107 {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe},
108 {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe},
109 {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe},
110 {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe},
111 {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe},
112 {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe},
113 {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe},
114 {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe},
115 {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe},
116 {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe},
117 {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe},
118 {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x0000ffff},
119};
120
121/* slcg ltc */
122static const struct gating_desc gp10b_slcg_ltc[] = {
123 {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe},
124 {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe},
125};
126
127/* slcg perf */
128static const struct gating_desc gp10b_slcg_perf[] = {
129 {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000},
130 {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000},
131 {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000},
132 {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000},
133};
134
135/* slcg PriRing */
136static const struct gating_desc gp10b_slcg_priring[] = {
137 {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001},
138};
139
140/* slcg pwr_csb */
141static const struct gating_desc gp10b_slcg_pwr_csb[] = {
142 {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe},
143 {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f},
144 {.addr = 0x00000a74, .prod = 0x00004000, .disable = 0x00007ffe},
145 {.addr = 0x000016b8, .prod = 0x00000000, .disable = 0x0000000f},
146};
147
148/* slcg pmu */
149static const struct gating_desc gp10b_slcg_pmu[] = {
150 {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe},
151 {.addr = 0x0010aa74, .prod = 0x00004000, .disable = 0x00007ffe},
152 {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f},
153};
154
155/* therm gr */
156static const struct gating_desc gp10b_slcg_therm[] = {
157 {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f},
158};
159
160/* slcg Xbar */
161static const struct gating_desc gp10b_slcg_xbar[] = {
162 {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe},
163 {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe},
164};
165
166/* blcg bus */
167static const struct gating_desc gp10b_blcg_bus[] = {
168 {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000},
169};
170
171/* blcg ce */
172static const struct gating_desc gp10b_blcg_ce[] = {
173 {.addr = 0x00104200, .prod = 0x00008242, .disable = 0x00000000},
174};
175
176/* blcg ctxsw prog */
177static const struct gating_desc gp10b_blcg_ctxsw_prog[] = {
178};
179
180/* blcg fb */
181static const struct gating_desc gp10b_blcg_fb[] = {
182 {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000},
183 {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000},
184 {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000},
185 {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000},
186 {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000},
187};
188
189/* blcg fifo */
190static const struct gating_desc gp10b_blcg_fifo[] = {
191 {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000},
192};
193
194/* blcg gr */
195static const struct gating_desc gp10b_blcg_gr[] = {
196 {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000},
197 {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000},
198 {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000},
199 {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000},
200 {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000},
201 {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000},
202 {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000},
203 {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000},
204 {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000},
205 {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000},
206 {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000},
207 {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000},
208 {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000},
209 {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000},
210 {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000},
211 {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000},
212 {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000},
213 {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000},
214 {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000},
215 {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000},
216 {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000},
217 {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000},
218 {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000},
219 {.addr = 0x00418e0c, .prod = 0x00008444, .disable = 0x00000000},
220 {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000},
221 {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000},
222 {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000},
223 {.addr = 0x00419a40, .prod = 0x0000c242, .disable = 0x00000000},
224 {.addr = 0x00419a48, .prod = 0x0000c242, .disable = 0x00000000},
225 {.addr = 0x00419a50, .prod = 0x0000c242, .disable = 0x00000000},
226 {.addr = 0x00419a58, .prod = 0x0000c242, .disable = 0x00000000},
227 {.addr = 0x00419a60, .prod = 0x0000c242, .disable = 0x00000000},
228 {.addr = 0x00419a68, .prod = 0x0000c242, .disable = 0x00000000},
229 {.addr = 0x00419a70, .prod = 0x0000c242, .disable = 0x00000000},
230 {.addr = 0x00419a78, .prod = 0x0000c242, .disable = 0x00000000},
231 {.addr = 0x00419a80, .prod = 0x0000c242, .disable = 0x00000000},
232 {.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000},
233 {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000},
234 {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000},
235 {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000},
236 {.addr = 0x00419fd0, .prod = 0x0000c044, .disable = 0x00000000},
237 {.addr = 0x00419fd8, .prod = 0x0000c046, .disable = 0x00000000},
238 {.addr = 0x00419fe0, .prod = 0x0000c044, .disable = 0x00000000},
239 {.addr = 0x00419fe8, .prod = 0x0000c042, .disable = 0x00000000},
240 {.addr = 0x00419ff0, .prod = 0x0000c045, .disable = 0x00000000},
241 {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000},
242 {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000},
243 {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000},
244 {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000},
245 {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000},
246 {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000},
247 {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000},
248 {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000},
249};
250
251/* blcg ltc */
252static const struct gating_desc gp10b_blcg_ltc[] = {
253 {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000},
254 {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000},
255 {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000},
256 {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000},
257};
258
259/* blcg pwr_csb */
260static const struct gating_desc gp10b_blcg_pwr_csb[] = {
261 {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000},
262};
263
264/* blcg pmu */
265static const struct gating_desc gp10b_blcg_pmu[] = {
266 {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000},
267};
268
269/* blcg Xbar */
270static const struct gating_desc gp10b_blcg_xbar[] = {
271 {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000},
272 {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000},
273};
274
275/* pg gr */
276static const struct gating_desc gp10b_pg_gr[] = {
277};
278
279/* inline functions */
280void gp10b_slcg_bus_load_gating_prod(struct gk20a *g,
281 bool prod)
282{
283 u32 i;
284 u32 size = sizeof(gp10b_slcg_bus) / sizeof(struct gating_desc);
285
286 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
287 return;
288
289 for (i = 0; i < size; i++) {
290 if (prod)
291 gk20a_writel(g, gp10b_slcg_bus[i].addr,
292 gp10b_slcg_bus[i].prod);
293 else
294 gk20a_writel(g, gp10b_slcg_bus[i].addr,
295 gp10b_slcg_bus[i].disable);
296 }
297}
298
299void gp10b_slcg_ce2_load_gating_prod(struct gk20a *g,
300 bool prod)
301{
302 u32 i;
303 u32 size = sizeof(gp10b_slcg_ce2) / sizeof(struct gating_desc);
304
305 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
306 return;
307
308 for (i = 0; i < size; i++) {
309 if (prod)
310 gk20a_writel(g, gp10b_slcg_ce2[i].addr,
311 gp10b_slcg_ce2[i].prod);
312 else
313 gk20a_writel(g, gp10b_slcg_ce2[i].addr,
314 gp10b_slcg_ce2[i].disable);
315 }
316}
317
318void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g,
319 bool prod)
320{
321 u32 i;
322 u32 size = sizeof(gp10b_slcg_chiplet) / sizeof(struct gating_desc);
323
324 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
325 return;
326
327 for (i = 0; i < size; i++) {
328 if (prod)
329 gk20a_writel(g, gp10b_slcg_chiplet[i].addr,
330 gp10b_slcg_chiplet[i].prod);
331 else
332 gk20a_writel(g, gp10b_slcg_chiplet[i].addr,
333 gp10b_slcg_chiplet[i].disable);
334 }
335}
336
337void gp10b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
338 bool prod)
339{
340}
341
342void gp10b_slcg_fb_load_gating_prod(struct gk20a *g,
343 bool prod)
344{
345 u32 i;
346 u32 size = sizeof(gp10b_slcg_fb) / sizeof(struct gating_desc);
347
348 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
349 return;
350
351 for (i = 0; i < size; i++) {
352 if (prod)
353 gk20a_writel(g, gp10b_slcg_fb[i].addr,
354 gp10b_slcg_fb[i].prod);
355 else
356 gk20a_writel(g, gp10b_slcg_fb[i].addr,
357 gp10b_slcg_fb[i].disable);
358 }
359}
360
361void gp10b_slcg_fifo_load_gating_prod(struct gk20a *g,
362 bool prod)
363{
364 u32 i;
365 u32 size = sizeof(gp10b_slcg_fifo) / sizeof(struct gating_desc);
366
367 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
368 return;
369
370 for (i = 0; i < size; i++) {
371 if (prod)
372 gk20a_writel(g, gp10b_slcg_fifo[i].addr,
373 gp10b_slcg_fifo[i].prod);
374 else
375 gk20a_writel(g, gp10b_slcg_fifo[i].addr,
376 gp10b_slcg_fifo[i].disable);
377 }
378}
379
380void gr_gp10b_slcg_gr_load_gating_prod(struct gk20a *g,
381 bool prod)
382{
383 u32 i;
384 u32 size = sizeof(gp10b_slcg_gr) / sizeof(struct gating_desc);
385
386 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
387 return;
388
389 for (i = 0; i < size; i++) {
390 if (prod)
391 gk20a_writel(g, gp10b_slcg_gr[i].addr,
392 gp10b_slcg_gr[i].prod);
393 else
394 gk20a_writel(g, gp10b_slcg_gr[i].addr,
395 gp10b_slcg_gr[i].disable);
396 }
397}
398
399void ltc_gp10b_slcg_ltc_load_gating_prod(struct gk20a *g,
400 bool prod)
401{
402 u32 i;
403 u32 size = sizeof(gp10b_slcg_ltc) / sizeof(struct gating_desc);
404
405 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
406 return;
407
408 for (i = 0; i < size; i++) {
409 if (prod)
410 gk20a_writel(g, gp10b_slcg_ltc[i].addr,
411 gp10b_slcg_ltc[i].prod);
412 else
413 gk20a_writel(g, gp10b_slcg_ltc[i].addr,
414 gp10b_slcg_ltc[i].disable);
415 }
416}
417
418void gp10b_slcg_perf_load_gating_prod(struct gk20a *g,
419 bool prod)
420{
421 u32 i;
422 u32 size = sizeof(gp10b_slcg_perf) / sizeof(struct gating_desc);
423
424 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
425 return;
426
427 for (i = 0; i < size; i++) {
428 if (prod)
429 gk20a_writel(g, gp10b_slcg_perf[i].addr,
430 gp10b_slcg_perf[i].prod);
431 else
432 gk20a_writel(g, gp10b_slcg_perf[i].addr,
433 gp10b_slcg_perf[i].disable);
434 }
435}
436
437void gp10b_slcg_priring_load_gating_prod(struct gk20a *g,
438 bool prod)
439{
440 u32 i;
441 u32 size = sizeof(gp10b_slcg_priring) / sizeof(struct gating_desc);
442
443 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
444 return;
445
446 for (i = 0; i < size; i++) {
447 if (prod)
448 gk20a_writel(g, gp10b_slcg_priring[i].addr,
449 gp10b_slcg_priring[i].prod);
450 else
451 gk20a_writel(g, gp10b_slcg_priring[i].addr,
452 gp10b_slcg_priring[i].disable);
453 }
454}
455
456void gp10b_slcg_pwr_csb_load_gating_prod(struct gk20a *g,
457 bool prod)
458{
459 u32 i;
460 u32 size = sizeof(gp10b_slcg_pwr_csb) / sizeof(struct gating_desc);
461
462 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
463 return;
464
465 for (i = 0; i < size; i++) {
466 if (prod)
467 gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr,
468 gp10b_slcg_pwr_csb[i].prod);
469 else
470 gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr,
471 gp10b_slcg_pwr_csb[i].disable);
472 }
473}
474
475void gp10b_slcg_pmu_load_gating_prod(struct gk20a *g,
476 bool prod)
477{
478 u32 i;
479 u32 size = sizeof(gp10b_slcg_pmu) / sizeof(struct gating_desc);
480
481 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
482 return;
483
484 for (i = 0; i < size; i++) {
485 if (prod)
486 gk20a_writel(g, gp10b_slcg_pmu[i].addr,
487 gp10b_slcg_pmu[i].prod);
488 else
489 gk20a_writel(g, gp10b_slcg_pmu[i].addr,
490 gp10b_slcg_pmu[i].disable);
491 }
492}
493
494void gp10b_slcg_therm_load_gating_prod(struct gk20a *g,
495 bool prod)
496{
497 u32 i;
498 u32 size = sizeof(gp10b_slcg_therm) / sizeof(struct gating_desc);
499
500 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
501 return;
502
503 for (i = 0; i < size; i++) {
504 if (prod)
505 gk20a_writel(g, gp10b_slcg_therm[i].addr,
506 gp10b_slcg_therm[i].prod);
507 else
508 gk20a_writel(g, gp10b_slcg_therm[i].addr,
509 gp10b_slcg_therm[i].disable);
510 }
511}
512
513void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g,
514 bool prod)
515{
516 u32 i;
517 u32 size = sizeof(gp10b_slcg_xbar) / sizeof(struct gating_desc);
518
519 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
520 return;
521
522 for (i = 0; i < size; i++) {
523 if (prod)
524 gk20a_writel(g, gp10b_slcg_xbar[i].addr,
525 gp10b_slcg_xbar[i].prod);
526 else
527 gk20a_writel(g, gp10b_slcg_xbar[i].addr,
528 gp10b_slcg_xbar[i].disable);
529 }
530}
531
532void gp10b_blcg_bus_load_gating_prod(struct gk20a *g,
533 bool prod)
534{
535 u32 i;
536 u32 size = sizeof(gp10b_blcg_bus) / sizeof(struct gating_desc);
537
538 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
539 return;
540
541 for (i = 0; i < size; i++) {
542 if (prod)
543 gk20a_writel(g, gp10b_blcg_bus[i].addr,
544 gp10b_blcg_bus[i].prod);
545 else
546 gk20a_writel(g, gp10b_blcg_bus[i].addr,
547 gp10b_blcg_bus[i].disable);
548 }
549}
550
551void gp10b_blcg_ce_load_gating_prod(struct gk20a *g,
552 bool prod)
553{
554 u32 i;
555 u32 size = sizeof(gp10b_blcg_ce) / sizeof(struct gating_desc);
556
557 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
558 return;
559
560 for (i = 0; i < size; i++) {
561 if (prod)
562 gk20a_writel(g, gp10b_blcg_ce[i].addr,
563 gp10b_blcg_ce[i].prod);
564 else
565 gk20a_writel(g, gp10b_blcg_ce[i].addr,
566 gp10b_blcg_ce[i].disable);
567 }
568}
569
570void gp10b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
571 bool prod)
572{
573 u32 i;
574 u32 size = sizeof(gp10b_blcg_ctxsw_prog) / sizeof(struct gating_desc);
575
576 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
577 return;
578
579 for (i = 0; i < size; i++) {
580 if (prod)
581 gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr,
582 gp10b_blcg_ctxsw_prog[i].prod);
583 else
584 gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr,
585 gp10b_blcg_ctxsw_prog[i].disable);
586 }
587}
588
589void gp10b_blcg_fb_load_gating_prod(struct gk20a *g,
590 bool prod)
591{
592 u32 i;
593 u32 size = sizeof(gp10b_blcg_fb) / sizeof(struct gating_desc);
594
595 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
596 return;
597
598 for (i = 0; i < size; i++) {
599 if (prod)
600 gk20a_writel(g, gp10b_blcg_fb[i].addr,
601 gp10b_blcg_fb[i].prod);
602 else
603 gk20a_writel(g, gp10b_blcg_fb[i].addr,
604 gp10b_blcg_fb[i].disable);
605 }
606}
607
608void gp10b_blcg_fifo_load_gating_prod(struct gk20a *g,
609 bool prod)
610{
611 u32 i;
612 u32 size = sizeof(gp10b_blcg_fifo) / sizeof(struct gating_desc);
613
614 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
615 return;
616
617 for (i = 0; i < size; i++) {
618 if (prod)
619 gk20a_writel(g, gp10b_blcg_fifo[i].addr,
620 gp10b_blcg_fifo[i].prod);
621 else
622 gk20a_writel(g, gp10b_blcg_fifo[i].addr,
623 gp10b_blcg_fifo[i].disable);
624 }
625}
626
627void gp10b_blcg_gr_load_gating_prod(struct gk20a *g,
628 bool prod)
629{
630 u32 i;
631 u32 size = sizeof(gp10b_blcg_gr) / sizeof(struct gating_desc);
632
633 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
634 return;
635
636 for (i = 0; i < size; i++) {
637 if (prod)
638 gk20a_writel(g, gp10b_blcg_gr[i].addr,
639 gp10b_blcg_gr[i].prod);
640 else
641 gk20a_writel(g, gp10b_blcg_gr[i].addr,
642 gp10b_blcg_gr[i].disable);
643 }
644}
645
646void gp10b_blcg_ltc_load_gating_prod(struct gk20a *g,
647 bool prod)
648{
649 u32 i;
650 u32 size = sizeof(gp10b_blcg_ltc) / sizeof(struct gating_desc);
651
652 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
653 return;
654
655 for (i = 0; i < size; i++) {
656 if (prod)
657 gk20a_writel(g, gp10b_blcg_ltc[i].addr,
658 gp10b_blcg_ltc[i].prod);
659 else
660 gk20a_writel(g, gp10b_blcg_ltc[i].addr,
661 gp10b_blcg_ltc[i].disable);
662 }
663}
664
665void gp10b_blcg_pwr_csb_load_gating_prod(struct gk20a *g,
666 bool prod)
667{
668 u32 i;
669 u32 size = sizeof(gp10b_blcg_pwr_csb) / sizeof(struct gating_desc);
670
671 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
672 return;
673
674 for (i = 0; i < size; i++) {
675 if (prod)
676 gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr,
677 gp10b_blcg_pwr_csb[i].prod);
678 else
679 gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr,
680 gp10b_blcg_pwr_csb[i].disable);
681 }
682}
683
684void gp10b_blcg_pmu_load_gating_prod(struct gk20a *g,
685 bool prod)
686{
687 u32 i;
688 u32 size = sizeof(gp10b_blcg_pmu) / sizeof(struct gating_desc);
689
690 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
691 return;
692
693 for (i = 0; i < size; i++) {
694 if (prod)
695 gk20a_writel(g, gp10b_blcg_pmu[i].addr,
696 gp10b_blcg_pmu[i].prod);
697 else
698 gk20a_writel(g, gp10b_blcg_pmu[i].addr,
699 gp10b_blcg_pmu[i].disable);
700 }
701}
702
703void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g,
704 bool prod)
705{
706 u32 i;
707 u32 size = sizeof(gp10b_blcg_xbar) / sizeof(struct gating_desc);
708
709 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
710 return;
711
712 for (i = 0; i < size; i++) {
713 if (prod)
714 gk20a_writel(g, gp10b_blcg_xbar[i].addr,
715 gp10b_blcg_xbar[i].prod);
716 else
717 gk20a_writel(g, gp10b_blcg_xbar[i].addr,
718 gp10b_blcg_xbar[i].disable);
719 }
720}
721
722void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g,
723 bool prod)
724{
725 u32 i;
726 u32 size = sizeof(gp10b_pg_gr) / sizeof(struct gating_desc);
727
728 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
729 return;
730
731 for (i = 0; i < size; i++) {
732 if (prod)
733 gk20a_writel(g, gp10b_pg_gr[i].addr,
734 gp10b_pg_gr[i].prod);
735 else
736 gk20a_writel(g, gp10b_pg_gr[i].addr,
737 gp10b_pg_gr[i].disable);
738 }
739}
740
741#endif /* __gp10b_gating_reglist_h__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-22 15:10:57 -0400