diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c | 640 |
1 files changed, 640 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c new file mode 100644 index 00000000..563819de --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c | |||
@@ -0,0 +1,640 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License. | ||
7 | * | ||
8 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License along | ||
14 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
15 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | ||
16 | * | ||
17 | * This file is autogenerated. Do not edit. | ||
18 | */ | ||
19 | |||
20 | #ifndef __gp10b_gating_reglist_h__ | ||
21 | #define __gp10b_gating_reglist_h__ | ||
22 | |||
23 | #include <linux/types.h> | ||
24 | #include "gp10b_gating_reglist.h" | ||
25 | |||
26 | struct gating_desc { | ||
27 | u32 addr; | ||
28 | u32 prod; | ||
29 | u32 disable; | ||
30 | }; | ||
31 | /* slcg bus */ | ||
32 | static const struct gating_desc gp10b_slcg_bus[] = { | ||
33 | {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, | ||
34 | }; | ||
35 | |||
36 | /* slcg ce2 */ | ||
37 | static const struct gating_desc gp10b_slcg_ce2[] = { | ||
38 | {.addr = 0x00104204, .prod = 0x00000000, .disable = 0x000007fe}, | ||
39 | }; | ||
40 | |||
41 | /* slcg chiplet */ | ||
42 | static const struct gating_desc gp10b_slcg_chiplet[] = { | ||
43 | {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
44 | {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
45 | {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
46 | {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, | ||
47 | }; | ||
48 | |||
49 | /* slcg fb */ | ||
50 | static const struct gating_desc gp10b_slcg_fb[] = { | ||
51 | {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
52 | {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
53 | }; | ||
54 | |||
55 | /* slcg fifo */ | ||
56 | static const struct gating_desc gp10b_slcg_fifo[] = { | ||
57 | {.addr = 0x000026ac, .prod = 0x00000f40, .disable = 0x0001fffe}, | ||
58 | }; | ||
59 | |||
60 | /* slcg gr */ | ||
61 | static const struct gating_desc gp10b_slcg_gr[] = { | ||
62 | {.addr = 0x004041f4, .prod = 0x00000002, .disable = 0x03fffffe}, | ||
63 | {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
64 | {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x03fffffe}, | ||
65 | {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, | ||
66 | {.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
67 | {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, | ||
68 | {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, | ||
69 | {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, | ||
70 | {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe}, | ||
71 | {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
72 | {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x03fffffe}, | ||
73 | {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, | ||
74 | {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
75 | {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, | ||
76 | {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x0000003e}, | ||
77 | {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, | ||
78 | {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
79 | {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, | ||
80 | {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
81 | {.addr = 0x00418c74, .prod = 0xffffffc0, .disable = 0xfffffffe}, | ||
82 | {.addr = 0x00418cf4, .prod = 0xfffffffc, .disable = 0xfffffffe}, | ||
83 | {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, | ||
84 | {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, | ||
85 | {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, | ||
86 | {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, | ||
87 | {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
88 | {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x0000ffff}, | ||
89 | {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e}, | ||
90 | {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
91 | {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e}, | ||
92 | {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e}, | ||
93 | {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe}, | ||
94 | {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e}, | ||
95 | {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e}, | ||
96 | {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e}, | ||
97 | {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e}, | ||
98 | {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, | ||
99 | {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe}, | ||
100 | {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe}, | ||
101 | {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, | ||
102 | {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe}, | ||
103 | {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe}, | ||
104 | {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe}, | ||
105 | {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe}, | ||
106 | {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
107 | {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, | ||
108 | {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, | ||
109 | {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe}, | ||
110 | {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
111 | {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
112 | {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
113 | {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x0000ffff}, | ||
114 | }; | ||
115 | |||
116 | /* slcg ltc */ | ||
117 | static const struct gating_desc gp10b_slcg_ltc[] = { | ||
118 | {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
119 | {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
120 | }; | ||
121 | |||
122 | /* slcg perf */ | ||
123 | static const struct gating_desc gp10b_slcg_perf[] = { | ||
124 | {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000}, | ||
125 | {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000}, | ||
126 | {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000}, | ||
127 | {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000}, | ||
128 | }; | ||
129 | |||
130 | /* slcg PriRing */ | ||
131 | static const struct gating_desc gp10b_slcg_priring[] = { | ||
132 | {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, | ||
133 | }; | ||
134 | |||
135 | /* slcg pwr_csb */ | ||
136 | static const struct gating_desc gp10b_slcg_pwr_csb[] = { | ||
137 | {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
138 | {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, | ||
139 | {.addr = 0x00000a74, .prod = 0x00004000, .disable = 0x00007ffe}, | ||
140 | {.addr = 0x000016b8, .prod = 0x00000000, .disable = 0x0000000f}, | ||
141 | }; | ||
142 | |||
143 | /* slcg pmu */ | ||
144 | static const struct gating_desc gp10b_slcg_pmu[] = { | ||
145 | {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
146 | {.addr = 0x0010aa74, .prod = 0x00004000, .disable = 0x00007ffe}, | ||
147 | {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, | ||
148 | }; | ||
149 | |||
150 | /* therm gr */ | ||
151 | static const struct gating_desc gp10b_slcg_therm[] = { | ||
152 | {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, | ||
153 | }; | ||
154 | |||
155 | /* slcg Xbar */ | ||
156 | static const struct gating_desc gp10b_slcg_xbar[] = { | ||
157 | {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
158 | {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
159 | }; | ||
160 | |||
161 | /* blcg bus */ | ||
162 | static const struct gating_desc gp10b_blcg_bus[] = { | ||
163 | {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, | ||
164 | }; | ||
165 | |||
166 | /* blcg ce */ | ||
167 | static const struct gating_desc gp10b_blcg_ce[] = { | ||
168 | {.addr = 0x00104200, .prod = 0x00008242, .disable = 0x00000000}, | ||
169 | }; | ||
170 | |||
171 | /* blcg ctxsw prog */ | ||
172 | static const struct gating_desc gp10b_blcg_ctxsw_prog[] = { | ||
173 | }; | ||
174 | |||
175 | /* blcg fb */ | ||
176 | static const struct gating_desc gp10b_blcg_fb[] = { | ||
177 | {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, | ||
178 | {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, | ||
179 | {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, | ||
180 | {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, | ||
181 | {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, | ||
182 | }; | ||
183 | |||
184 | /* blcg fifo */ | ||
185 | static const struct gating_desc gp10b_blcg_fifo[] = { | ||
186 | {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000}, | ||
187 | }; | ||
188 | |||
189 | /* blcg gr */ | ||
190 | static const struct gating_desc gp10b_blcg_gr[] = { | ||
191 | {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, | ||
192 | {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, | ||
193 | {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, | ||
194 | {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, | ||
195 | {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, | ||
196 | {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, | ||
197 | {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, | ||
198 | {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, | ||
199 | {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, | ||
200 | {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
201 | {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, | ||
202 | {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, | ||
203 | {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, | ||
204 | {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, | ||
205 | {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, | ||
206 | {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, | ||
207 | {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, | ||
208 | {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, | ||
209 | {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, | ||
210 | {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
211 | {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
212 | {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
213 | {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, | ||
214 | {.addr = 0x00418e0c, .prod = 0x00008444, .disable = 0x00000000}, | ||
215 | {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, | ||
216 | {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, | ||
217 | {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, | ||
218 | {.addr = 0x00419a40, .prod = 0x0000c242, .disable = 0x00000000}, | ||
219 | {.addr = 0x00419a48, .prod = 0x0000c242, .disable = 0x00000000}, | ||
220 | {.addr = 0x00419a50, .prod = 0x0000c242, .disable = 0x00000000}, | ||
221 | {.addr = 0x00419a58, .prod = 0x0000c242, .disable = 0x00000000}, | ||
222 | {.addr = 0x00419a60, .prod = 0x0000c242, .disable = 0x00000000}, | ||
223 | {.addr = 0x00419a68, .prod = 0x0000c242, .disable = 0x00000000}, | ||
224 | {.addr = 0x00419a70, .prod = 0x0000c242, .disable = 0x00000000}, | ||
225 | {.addr = 0x00419a78, .prod = 0x0000c242, .disable = 0x00000000}, | ||
226 | {.addr = 0x00419a80, .prod = 0x0000c242, .disable = 0x00000000}, | ||
227 | {.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000}, | ||
228 | {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000}, | ||
229 | {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000}, | ||
230 | {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
231 | {.addr = 0x00419fd0, .prod = 0x0000c044, .disable = 0x00000000}, | ||
232 | {.addr = 0x00419fd8, .prod = 0x0000c046, .disable = 0x00000000}, | ||
233 | {.addr = 0x00419fe0, .prod = 0x0000c044, .disable = 0x00000000}, | ||
234 | {.addr = 0x00419fe8, .prod = 0x0000c042, .disable = 0x00000000}, | ||
235 | {.addr = 0x00419ff0, .prod = 0x0000c045, .disable = 0x00000000}, | ||
236 | {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000}, | ||
237 | {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000}, | ||
238 | {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, | ||
239 | {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, | ||
240 | {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
241 | {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, | ||
242 | {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, | ||
243 | {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, | ||
244 | }; | ||
245 | |||
246 | /* blcg ltc */ | ||
247 | static const struct gating_desc gp10b_blcg_ltc[] = { | ||
248 | {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, | ||
249 | {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, | ||
250 | {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, | ||
251 | {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, | ||
252 | }; | ||
253 | |||
254 | /* blcg pwr_csb */ | ||
255 | static const struct gating_desc gp10b_blcg_pwr_csb[] = { | ||
256 | {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, | ||
257 | }; | ||
258 | |||
259 | /* blcg pmu */ | ||
260 | static const struct gating_desc gp10b_blcg_pmu[] = { | ||
261 | {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, | ||
262 | }; | ||
263 | |||
264 | /* blcg Xbar */ | ||
265 | static const struct gating_desc gp10b_blcg_xbar[] = { | ||
266 | {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, | ||
267 | {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, | ||
268 | }; | ||
269 | |||
270 | /* pg gr */ | ||
271 | static const struct gating_desc gp10b_pg_gr[] = { | ||
272 | }; | ||
273 | |||
274 | /* inline functions */ | ||
275 | void gp10b_slcg_bus_load_gating_prod(struct gk20a *g, | ||
276 | bool prod) | ||
277 | { | ||
278 | u32 i; | ||
279 | u32 size = sizeof(gp10b_slcg_bus) / sizeof(struct gating_desc); | ||
280 | for (i = 0; i < size; i++) { | ||
281 | if (prod) | ||
282 | gk20a_writel(g, gp10b_slcg_bus[i].addr, | ||
283 | gp10b_slcg_bus[i].prod); | ||
284 | else | ||
285 | gk20a_writel(g, gp10b_slcg_bus[i].addr, | ||
286 | gp10b_slcg_bus[i].disable); | ||
287 | } | ||
288 | } | ||
289 | |||
290 | void gp10b_slcg_ce2_load_gating_prod(struct gk20a *g, | ||
291 | bool prod) | ||
292 | { | ||
293 | u32 i; | ||
294 | u32 size = sizeof(gp10b_slcg_ce2) / sizeof(struct gating_desc); | ||
295 | for (i = 0; i < size; i++) { | ||
296 | if (prod) | ||
297 | gk20a_writel(g, gp10b_slcg_ce2[i].addr, | ||
298 | gp10b_slcg_ce2[i].prod); | ||
299 | else | ||
300 | gk20a_writel(g, gp10b_slcg_ce2[i].addr, | ||
301 | gp10b_slcg_ce2[i].disable); | ||
302 | } | ||
303 | } | ||
304 | |||
305 | void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g, | ||
306 | bool prod) | ||
307 | { | ||
308 | u32 i; | ||
309 | u32 size = sizeof(gp10b_slcg_chiplet) / sizeof(struct gating_desc); | ||
310 | for (i = 0; i < size; i++) { | ||
311 | if (prod) | ||
312 | gk20a_writel(g, gp10b_slcg_chiplet[i].addr, | ||
313 | gp10b_slcg_chiplet[i].prod); | ||
314 | else | ||
315 | gk20a_writel(g, gp10b_slcg_chiplet[i].addr, | ||
316 | gp10b_slcg_chiplet[i].disable); | ||
317 | } | ||
318 | } | ||
319 | |||
320 | void gp10b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
321 | bool prod) | ||
322 | { | ||
323 | } | ||
324 | |||
325 | void gp10b_slcg_fb_load_gating_prod(struct gk20a *g, | ||
326 | bool prod) | ||
327 | { | ||
328 | u32 i; | ||
329 | u32 size = sizeof(gp10b_slcg_fb) / sizeof(struct gating_desc); | ||
330 | for (i = 0; i < size; i++) { | ||
331 | if (prod) | ||
332 | gk20a_writel(g, gp10b_slcg_fb[i].addr, | ||
333 | gp10b_slcg_fb[i].prod); | ||
334 | else | ||
335 | gk20a_writel(g, gp10b_slcg_fb[i].addr, | ||
336 | gp10b_slcg_fb[i].disable); | ||
337 | } | ||
338 | } | ||
339 | |||
340 | void gp10b_slcg_fifo_load_gating_prod(struct gk20a *g, | ||
341 | bool prod) | ||
342 | { | ||
343 | u32 i; | ||
344 | u32 size = sizeof(gp10b_slcg_fifo) / sizeof(struct gating_desc); | ||
345 | for (i = 0; i < size; i++) { | ||
346 | if (prod) | ||
347 | gk20a_writel(g, gp10b_slcg_fifo[i].addr, | ||
348 | gp10b_slcg_fifo[i].prod); | ||
349 | else | ||
350 | gk20a_writel(g, gp10b_slcg_fifo[i].addr, | ||
351 | gp10b_slcg_fifo[i].disable); | ||
352 | } | ||
353 | } | ||
354 | |||
355 | void gr_gp10b_slcg_gr_load_gating_prod(struct gk20a *g, | ||
356 | bool prod) | ||
357 | { | ||
358 | u32 i; | ||
359 | u32 size = sizeof(gp10b_slcg_gr) / sizeof(struct gating_desc); | ||
360 | for (i = 0; i < size; i++) { | ||
361 | if (prod) | ||
362 | gk20a_writel(g, gp10b_slcg_gr[i].addr, | ||
363 | gp10b_slcg_gr[i].prod); | ||
364 | else | ||
365 | gk20a_writel(g, gp10b_slcg_gr[i].addr, | ||
366 | gp10b_slcg_gr[i].disable); | ||
367 | } | ||
368 | } | ||
369 | |||
370 | void ltc_gp10b_slcg_ltc_load_gating_prod(struct gk20a *g, | ||
371 | bool prod) | ||
372 | { | ||
373 | u32 i; | ||
374 | u32 size = sizeof(gp10b_slcg_ltc) / sizeof(struct gating_desc); | ||
375 | for (i = 0; i < size; i++) { | ||
376 | if (prod) | ||
377 | gk20a_writel(g, gp10b_slcg_ltc[i].addr, | ||
378 | gp10b_slcg_ltc[i].prod); | ||
379 | else | ||
380 | gk20a_writel(g, gp10b_slcg_ltc[i].addr, | ||
381 | gp10b_slcg_ltc[i].disable); | ||
382 | } | ||
383 | } | ||
384 | |||
385 | void gp10b_slcg_perf_load_gating_prod(struct gk20a *g, | ||
386 | bool prod) | ||
387 | { | ||
388 | u32 i; | ||
389 | u32 size = sizeof(gp10b_slcg_perf) / sizeof(struct gating_desc); | ||
390 | for (i = 0; i < size; i++) { | ||
391 | if (prod) | ||
392 | gk20a_writel(g, gp10b_slcg_perf[i].addr, | ||
393 | gp10b_slcg_perf[i].prod); | ||
394 | else | ||
395 | gk20a_writel(g, gp10b_slcg_perf[i].addr, | ||
396 | gp10b_slcg_perf[i].disable); | ||
397 | } | ||
398 | } | ||
399 | |||
400 | void gp10b_slcg_priring_load_gating_prod(struct gk20a *g, | ||
401 | bool prod) | ||
402 | { | ||
403 | u32 i; | ||
404 | u32 size = sizeof(gp10b_slcg_priring) / sizeof(struct gating_desc); | ||
405 | for (i = 0; i < size; i++) { | ||
406 | if (prod) | ||
407 | gk20a_writel(g, gp10b_slcg_priring[i].addr, | ||
408 | gp10b_slcg_priring[i].prod); | ||
409 | else | ||
410 | gk20a_writel(g, gp10b_slcg_priring[i].addr, | ||
411 | gp10b_slcg_priring[i].disable); | ||
412 | } | ||
413 | } | ||
414 | |||
415 | void gp10b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, | ||
416 | bool prod) | ||
417 | { | ||
418 | u32 i; | ||
419 | u32 size = sizeof(gp10b_slcg_pwr_csb) / sizeof(struct gating_desc); | ||
420 | for (i = 0; i < size; i++) { | ||
421 | if (prod) | ||
422 | gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr, | ||
423 | gp10b_slcg_pwr_csb[i].prod); | ||
424 | else | ||
425 | gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr, | ||
426 | gp10b_slcg_pwr_csb[i].disable); | ||
427 | } | ||
428 | } | ||
429 | |||
430 | void gp10b_slcg_pmu_load_gating_prod(struct gk20a *g, | ||
431 | bool prod) | ||
432 | { | ||
433 | u32 i; | ||
434 | u32 size = sizeof(gp10b_slcg_pmu) / sizeof(struct gating_desc); | ||
435 | for (i = 0; i < size; i++) { | ||
436 | if (prod) | ||
437 | gk20a_writel(g, gp10b_slcg_pmu[i].addr, | ||
438 | gp10b_slcg_pmu[i].prod); | ||
439 | else | ||
440 | gk20a_writel(g, gp10b_slcg_pmu[i].addr, | ||
441 | gp10b_slcg_pmu[i].disable); | ||
442 | } | ||
443 | } | ||
444 | |||
445 | void gp10b_slcg_therm_load_gating_prod(struct gk20a *g, | ||
446 | bool prod) | ||
447 | { | ||
448 | u32 i; | ||
449 | u32 size = sizeof(gp10b_slcg_therm) / sizeof(struct gating_desc); | ||
450 | for (i = 0; i < size; i++) { | ||
451 | if (prod) | ||
452 | gk20a_writel(g, gp10b_slcg_therm[i].addr, | ||
453 | gp10b_slcg_therm[i].prod); | ||
454 | else | ||
455 | gk20a_writel(g, gp10b_slcg_therm[i].addr, | ||
456 | gp10b_slcg_therm[i].disable); | ||
457 | } | ||
458 | } | ||
459 | |||
460 | void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g, | ||
461 | bool prod) | ||
462 | { | ||
463 | u32 i; | ||
464 | u32 size = sizeof(gp10b_slcg_xbar) / sizeof(struct gating_desc); | ||
465 | for (i = 0; i < size; i++) { | ||
466 | if (prod) | ||
467 | gk20a_writel(g, gp10b_slcg_xbar[i].addr, | ||
468 | gp10b_slcg_xbar[i].prod); | ||
469 | else | ||
470 | gk20a_writel(g, gp10b_slcg_xbar[i].addr, | ||
471 | gp10b_slcg_xbar[i].disable); | ||
472 | } | ||
473 | } | ||
474 | |||
475 | void gp10b_blcg_bus_load_gating_prod(struct gk20a *g, | ||
476 | bool prod) | ||
477 | { | ||
478 | u32 i; | ||
479 | u32 size = sizeof(gp10b_blcg_bus) / sizeof(struct gating_desc); | ||
480 | for (i = 0; i < size; i++) { | ||
481 | if (prod) | ||
482 | gk20a_writel(g, gp10b_blcg_bus[i].addr, | ||
483 | gp10b_blcg_bus[i].prod); | ||
484 | else | ||
485 | gk20a_writel(g, gp10b_blcg_bus[i].addr, | ||
486 | gp10b_blcg_bus[i].disable); | ||
487 | } | ||
488 | } | ||
489 | |||
490 | void gp10b_blcg_ce_load_gating_prod(struct gk20a *g, | ||
491 | bool prod) | ||
492 | { | ||
493 | u32 i; | ||
494 | u32 size = sizeof(gp10b_blcg_ce) / sizeof(struct gating_desc); | ||
495 | for (i = 0; i < size; i++) { | ||
496 | if (prod) | ||
497 | gk20a_writel(g, gp10b_blcg_ce[i].addr, | ||
498 | gp10b_blcg_ce[i].prod); | ||
499 | else | ||
500 | gk20a_writel(g, gp10b_blcg_ce[i].addr, | ||
501 | gp10b_blcg_ce[i].disable); | ||
502 | } | ||
503 | } | ||
504 | |||
505 | void gp10b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
506 | bool prod) | ||
507 | { | ||
508 | u32 i; | ||
509 | u32 size = sizeof(gp10b_blcg_ctxsw_prog) / sizeof(struct gating_desc); | ||
510 | for (i = 0; i < size; i++) { | ||
511 | if (prod) | ||
512 | gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr, | ||
513 | gp10b_blcg_ctxsw_prog[i].prod); | ||
514 | else | ||
515 | gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr, | ||
516 | gp10b_blcg_ctxsw_prog[i].disable); | ||
517 | } | ||
518 | } | ||
519 | |||
520 | void gp10b_blcg_fb_load_gating_prod(struct gk20a *g, | ||
521 | bool prod) | ||
522 | { | ||
523 | u32 i; | ||
524 | u32 size = sizeof(gp10b_blcg_fb) / sizeof(struct gating_desc); | ||
525 | for (i = 0; i < size; i++) { | ||
526 | if (prod) | ||
527 | gk20a_writel(g, gp10b_blcg_fb[i].addr, | ||
528 | gp10b_blcg_fb[i].prod); | ||
529 | else | ||
530 | gk20a_writel(g, gp10b_blcg_fb[i].addr, | ||
531 | gp10b_blcg_fb[i].disable); | ||
532 | } | ||
533 | } | ||
534 | |||
535 | void gp10b_blcg_fifo_load_gating_prod(struct gk20a *g, | ||
536 | bool prod) | ||
537 | { | ||
538 | u32 i; | ||
539 | u32 size = sizeof(gp10b_blcg_fifo) / sizeof(struct gating_desc); | ||
540 | for (i = 0; i < size; i++) { | ||
541 | if (prod) | ||
542 | gk20a_writel(g, gp10b_blcg_fifo[i].addr, | ||
543 | gp10b_blcg_fifo[i].prod); | ||
544 | else | ||
545 | gk20a_writel(g, gp10b_blcg_fifo[i].addr, | ||
546 | gp10b_blcg_fifo[i].disable); | ||
547 | } | ||
548 | } | ||
549 | |||
550 | void gp10b_blcg_gr_load_gating_prod(struct gk20a *g, | ||
551 | bool prod) | ||
552 | { | ||
553 | u32 i; | ||
554 | u32 size = sizeof(gp10b_blcg_gr) / sizeof(struct gating_desc); | ||
555 | for (i = 0; i < size; i++) { | ||
556 | if (prod) | ||
557 | gk20a_writel(g, gp10b_blcg_gr[i].addr, | ||
558 | gp10b_blcg_gr[i].prod); | ||
559 | else | ||
560 | gk20a_writel(g, gp10b_blcg_gr[i].addr, | ||
561 | gp10b_blcg_gr[i].disable); | ||
562 | } | ||
563 | } | ||
564 | |||
565 | void gp10b_blcg_ltc_load_gating_prod(struct gk20a *g, | ||
566 | bool prod) | ||
567 | { | ||
568 | u32 i; | ||
569 | u32 size = sizeof(gp10b_blcg_ltc) / sizeof(struct gating_desc); | ||
570 | for (i = 0; i < size; i++) { | ||
571 | if (prod) | ||
572 | gk20a_writel(g, gp10b_blcg_ltc[i].addr, | ||
573 | gp10b_blcg_ltc[i].prod); | ||
574 | else | ||
575 | gk20a_writel(g, gp10b_blcg_ltc[i].addr, | ||
576 | gp10b_blcg_ltc[i].disable); | ||
577 | } | ||
578 | } | ||
579 | |||
580 | void gp10b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, | ||
581 | bool prod) | ||
582 | { | ||
583 | u32 i; | ||
584 | u32 size = sizeof(gp10b_blcg_pwr_csb) / sizeof(struct gating_desc); | ||
585 | for (i = 0; i < size; i++) { | ||
586 | if (prod) | ||
587 | gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr, | ||
588 | gp10b_blcg_pwr_csb[i].prod); | ||
589 | else | ||
590 | gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr, | ||
591 | gp10b_blcg_pwr_csb[i].disable); | ||
592 | } | ||
593 | } | ||
594 | |||
595 | void gp10b_blcg_pmu_load_gating_prod(struct gk20a *g, | ||
596 | bool prod) | ||
597 | { | ||
598 | u32 i; | ||
599 | u32 size = sizeof(gp10b_blcg_pmu) / sizeof(struct gating_desc); | ||
600 | for (i = 0; i < size; i++) { | ||
601 | if (prod) | ||
602 | gk20a_writel(g, gp10b_blcg_pmu[i].addr, | ||
603 | gp10b_blcg_pmu[i].prod); | ||
604 | else | ||
605 | gk20a_writel(g, gp10b_blcg_pmu[i].addr, | ||
606 | gp10b_blcg_pmu[i].disable); | ||
607 | } | ||
608 | } | ||
609 | |||
610 | void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g, | ||
611 | bool prod) | ||
612 | { | ||
613 | u32 i; | ||
614 | u32 size = sizeof(gp10b_blcg_xbar) / sizeof(struct gating_desc); | ||
615 | for (i = 0; i < size; i++) { | ||
616 | if (prod) | ||
617 | gk20a_writel(g, gp10b_blcg_xbar[i].addr, | ||
618 | gp10b_blcg_xbar[i].prod); | ||
619 | else | ||
620 | gk20a_writel(g, gp10b_blcg_xbar[i].addr, | ||
621 | gp10b_blcg_xbar[i].disable); | ||
622 | } | ||
623 | } | ||
624 | |||
625 | void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g, | ||
626 | bool prod) | ||
627 | { | ||
628 | u32 i; | ||
629 | u32 size = sizeof(gp10b_pg_gr) / sizeof(struct gating_desc); | ||
630 | for (i = 0; i < size; i++) { | ||
631 | if (prod) | ||
632 | gk20a_writel(g, gp10b_pg_gr[i].addr, | ||
633 | gp10b_pg_gr[i].prod); | ||
634 | else | ||
635 | gk20a_writel(g, gp10b_pg_gr[i].addr, | ||
636 | gp10b_pg_gr[i].disable); | ||
637 | } | ||
638 | } | ||
639 | |||
640 | #endif /* __gp10b_gating_reglist_h__ */ | ||