diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gp10b.c | 54 |
1 files changed, 27 insertions, 27 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b.c b/drivers/gpu/nvgpu/gp10b/gp10b.c index 769d6ef3..51dc4301 100644 --- a/drivers/gpu/nvgpu/gp10b/gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gp10b.c | |||
@@ -24,14 +24,15 @@ | |||
24 | 24 | ||
25 | #include "gk20a/gk20a.h" | 25 | #include "gk20a/gk20a.h" |
26 | 26 | ||
27 | #include <nvgpu/enabled.h> | ||
28 | |||
27 | #include "gp10b.h" | 29 | #include "gp10b.h" |
28 | 30 | ||
29 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> | 31 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> |
30 | #include <nvgpu/hw/gp10b/hw_gr_gp10b.h> | 32 | #include <nvgpu/hw/gp10b/hw_gr_gp10b.h> |
31 | 33 | ||
32 | static u64 gp10b_detect_ecc_enabled_units(struct gk20a *g) | 34 | static void gp10b_detect_ecc_enabled_units(struct gk20a *g) |
33 | { | 35 | { |
34 | u64 ecc_enabled_units = 0; | ||
35 | u32 opt_ecc_en = gk20a_readl(g, fuse_opt_ecc_en_r()); | 36 | u32 opt_ecc_en = gk20a_readl(g, fuse_opt_ecc_en_r()); |
36 | u32 opt_feature_fuses_override_disable = | 37 | u32 opt_feature_fuses_override_disable = |
37 | gk20a_readl(g, | 38 | gk20a_readl(g, |
@@ -41,23 +42,25 @@ static u64 gp10b_detect_ecc_enabled_units(struct gk20a *g) | |||
41 | gr_fecs_feature_override_ecc_r()); | 42 | gr_fecs_feature_override_ecc_r()); |
42 | 43 | ||
43 | if (opt_feature_fuses_override_disable) { | 44 | if (opt_feature_fuses_override_disable) { |
44 | if (opt_ecc_en) | 45 | if (opt_ecc_en) { |
45 | ecc_enabled_units = NVGPU_GPU_FLAGS_ALL_ECC_ENABLED; | 46 | __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_LRF, true); |
46 | else | 47 | __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_SHM, true); |
47 | ecc_enabled_units = 0; | 48 | __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_TEX, true); |
49 | __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_LTC, true); | ||
50 | } | ||
48 | } else { | 51 | } else { |
49 | /* SM LRF */ | 52 | /* SM LRF */ |
50 | if (gr_fecs_feature_override_ecc_sm_lrf_override_v( | 53 | if (gr_fecs_feature_override_ecc_sm_lrf_override_v( |
51 | fecs_feature_override_ecc)) { | 54 | fecs_feature_override_ecc)) { |
52 | if (gr_fecs_feature_override_ecc_sm_lrf_v( | 55 | if (gr_fecs_feature_override_ecc_sm_lrf_v( |
53 | fecs_feature_override_ecc)) { | 56 | fecs_feature_override_ecc)) { |
54 | ecc_enabled_units |= | 57 | __nvgpu_set_enabled(g, |
55 | NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF; | 58 | NVGPU_ECC_ENABLED_SM_LRF, true); |
56 | } | 59 | } |
57 | } else { | 60 | } else { |
58 | if (opt_ecc_en) { | 61 | if (opt_ecc_en) { |
59 | ecc_enabled_units |= | 62 | __nvgpu_set_enabled(g, |
60 | NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF; | 63 | NVGPU_ECC_ENABLED_SM_LRF, true); |
61 | } | 64 | } |
62 | } | 65 | } |
63 | 66 | ||
@@ -66,13 +69,13 @@ static u64 gp10b_detect_ecc_enabled_units(struct gk20a *g) | |||
66 | fecs_feature_override_ecc)) { | 69 | fecs_feature_override_ecc)) { |
67 | if (gr_fecs_feature_override_ecc_sm_shm_v( | 70 | if (gr_fecs_feature_override_ecc_sm_shm_v( |
68 | fecs_feature_override_ecc)) { | 71 | fecs_feature_override_ecc)) { |
69 | ecc_enabled_units |= | 72 | __nvgpu_set_enabled(g, |
70 | NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM; | 73 | NVGPU_ECC_ENABLED_SM_SHM, true); |
71 | } | 74 | } |
72 | } else { | 75 | } else { |
73 | if (opt_ecc_en) { | 76 | if (opt_ecc_en) { |
74 | ecc_enabled_units |= | 77 | __nvgpu_set_enabled(g, |
75 | NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM; | 78 | NVGPU_ECC_ENABLED_SM_SHM, true); |
76 | } | 79 | } |
77 | } | 80 | } |
78 | 81 | ||
@@ -81,13 +84,13 @@ static u64 gp10b_detect_ecc_enabled_units(struct gk20a *g) | |||
81 | fecs_feature_override_ecc)) { | 84 | fecs_feature_override_ecc)) { |
82 | if (gr_fecs_feature_override_ecc_tex_v( | 85 | if (gr_fecs_feature_override_ecc_tex_v( |
83 | fecs_feature_override_ecc)) { | 86 | fecs_feature_override_ecc)) { |
84 | ecc_enabled_units |= | 87 | __nvgpu_set_enabled(g, |
85 | NVGPU_GPU_FLAGS_ECC_ENABLED_TEX; | 88 | NVGPU_ECC_ENABLED_TEX, true); |
86 | } | 89 | } |
87 | } else { | 90 | } else { |
88 | if (opt_ecc_en) { | 91 | if (opt_ecc_en) { |
89 | ecc_enabled_units |= | 92 | __nvgpu_set_enabled(g, |
90 | NVGPU_GPU_FLAGS_ECC_ENABLED_TEX; | 93 | NVGPU_ECC_ENABLED_TEX, true); |
91 | } | 94 | } |
92 | } | 95 | } |
93 | 96 | ||
@@ -96,25 +99,22 @@ static u64 gp10b_detect_ecc_enabled_units(struct gk20a *g) | |||
96 | fecs_feature_override_ecc)) { | 99 | fecs_feature_override_ecc)) { |
97 | if (gr_fecs_feature_override_ecc_ltc_v( | 100 | if (gr_fecs_feature_override_ecc_ltc_v( |
98 | fecs_feature_override_ecc)) { | 101 | fecs_feature_override_ecc)) { |
99 | ecc_enabled_units |= | 102 | __nvgpu_set_enabled(g, |
100 | NVGPU_GPU_FLAGS_ECC_ENABLED_LTC; | 103 | NVGPU_ECC_ENABLED_LTC, true); |
101 | } | 104 | } |
102 | } else { | 105 | } else { |
103 | if (opt_ecc_en) { | 106 | if (opt_ecc_en) { |
104 | ecc_enabled_units |= | 107 | __nvgpu_set_enabled(g, |
105 | NVGPU_GPU_FLAGS_ECC_ENABLED_LTC; | 108 | NVGPU_ECC_ENABLED_LTC, true); |
106 | } | 109 | } |
107 | } | 110 | } |
108 | } | 111 | } |
109 | |||
110 | return ecc_enabled_units; | ||
111 | } | 112 | } |
112 | 113 | ||
113 | int gp10b_init_gpu_characteristics(struct gk20a *g) | 114 | int gp10b_init_gpu_characteristics(struct gk20a *g) |
114 | { | 115 | { |
115 | gk20a_init_gpu_characteristics(g); | 116 | gk20a_init_gpu_characteristics(g); |
116 | g->gpu_characteristics.flags |= gp10b_detect_ecc_enabled_units(g); | 117 | gp10b_detect_ecc_enabled_units(g); |
117 | g->gpu_characteristics.flags |= | 118 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_RESCHEDULE_RUNLIST, true); |
118 | NVGPU_GPU_FLAGS_SUPPORT_RESCHEDULE_RUNLIST; | ||
119 | return 0; | 119 | return 0; |
120 | } | 120 | } |