diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gp10b.c | 120 |
1 files changed, 120 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b.c b/drivers/gpu/nvgpu/gp10b/gp10b.c new file mode 100644 index 00000000..51dc4301 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/gp10b.c | |||
@@ -0,0 +1,120 @@ | |||
1 | /* | ||
2 | * GP10B Graphics | ||
3 | * | ||
4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include "gk20a/gk20a.h" | ||
26 | |||
27 | #include <nvgpu/enabled.h> | ||
28 | |||
29 | #include "gp10b.h" | ||
30 | |||
31 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> | ||
32 | #include <nvgpu/hw/gp10b/hw_gr_gp10b.h> | ||
33 | |||
34 | static void gp10b_detect_ecc_enabled_units(struct gk20a *g) | ||
35 | { | ||
36 | u32 opt_ecc_en = gk20a_readl(g, fuse_opt_ecc_en_r()); | ||
37 | u32 opt_feature_fuses_override_disable = | ||
38 | gk20a_readl(g, | ||
39 | fuse_opt_feature_fuses_override_disable_r()); | ||
40 | u32 fecs_feature_override_ecc = | ||
41 | gk20a_readl(g, | ||
42 | gr_fecs_feature_override_ecc_r()); | ||
43 | |||
44 | if (opt_feature_fuses_override_disable) { | ||
45 | if (opt_ecc_en) { | ||
46 | __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_LRF, true); | ||
47 | __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_SHM, true); | ||
48 | __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_TEX, true); | ||
49 | __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_LTC, true); | ||
50 | } | ||
51 | } else { | ||
52 | /* SM LRF */ | ||
53 | if (gr_fecs_feature_override_ecc_sm_lrf_override_v( | ||
54 | fecs_feature_override_ecc)) { | ||
55 | if (gr_fecs_feature_override_ecc_sm_lrf_v( | ||
56 | fecs_feature_override_ecc)) { | ||
57 | __nvgpu_set_enabled(g, | ||
58 | NVGPU_ECC_ENABLED_SM_LRF, true); | ||
59 | } | ||
60 | } else { | ||
61 | if (opt_ecc_en) { | ||
62 | __nvgpu_set_enabled(g, | ||
63 | NVGPU_ECC_ENABLED_SM_LRF, true); | ||
64 | } | ||
65 | } | ||
66 | |||
67 | /* SM SHM */ | ||
68 | if (gr_fecs_feature_override_ecc_sm_shm_override_v( | ||
69 | fecs_feature_override_ecc)) { | ||
70 | if (gr_fecs_feature_override_ecc_sm_shm_v( | ||
71 | fecs_feature_override_ecc)) { | ||
72 | __nvgpu_set_enabled(g, | ||
73 | NVGPU_ECC_ENABLED_SM_SHM, true); | ||
74 | } | ||
75 | } else { | ||
76 | if (opt_ecc_en) { | ||
77 | __nvgpu_set_enabled(g, | ||
78 | NVGPU_ECC_ENABLED_SM_SHM, true); | ||
79 | } | ||
80 | } | ||
81 | |||
82 | /* TEX */ | ||
83 | if (gr_fecs_feature_override_ecc_tex_override_v( | ||
84 | fecs_feature_override_ecc)) { | ||
85 | if (gr_fecs_feature_override_ecc_tex_v( | ||
86 | fecs_feature_override_ecc)) { | ||
87 | __nvgpu_set_enabled(g, | ||
88 | NVGPU_ECC_ENABLED_TEX, true); | ||
89 | } | ||
90 | } else { | ||
91 | if (opt_ecc_en) { | ||
92 | __nvgpu_set_enabled(g, | ||
93 | NVGPU_ECC_ENABLED_TEX, true); | ||
94 | } | ||
95 | } | ||
96 | |||
97 | /* LTC */ | ||
98 | if (gr_fecs_feature_override_ecc_ltc_override_v( | ||
99 | fecs_feature_override_ecc)) { | ||
100 | if (gr_fecs_feature_override_ecc_ltc_v( | ||
101 | fecs_feature_override_ecc)) { | ||
102 | __nvgpu_set_enabled(g, | ||
103 | NVGPU_ECC_ENABLED_LTC, true); | ||
104 | } | ||
105 | } else { | ||
106 | if (opt_ecc_en) { | ||
107 | __nvgpu_set_enabled(g, | ||
108 | NVGPU_ECC_ENABLED_LTC, true); | ||
109 | } | ||
110 | } | ||
111 | } | ||
112 | } | ||
113 | |||
114 | int gp10b_init_gpu_characteristics(struct gk20a *g) | ||
115 | { | ||
116 | gk20a_init_gpu_characteristics(g); | ||
117 | gp10b_detect_ecc_enabled_units(g); | ||
118 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_RESCHEDULE_RUNLIST, true); | ||
119 | return 0; | ||
120 | } | ||