diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/fuse_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/fuse_gp10b.c | 91 |
1 files changed, 91 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c b/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c new file mode 100644 index 00000000..7743c5df --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c | |||
@@ -0,0 +1,91 @@ | |||
1 | /* | ||
2 | * GP10B FUSE | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/types.h> | ||
26 | #include <nvgpu/fuse.h> | ||
27 | #include <nvgpu/enabled.h> | ||
28 | |||
29 | #include "gk20a/gk20a.h" | ||
30 | |||
31 | #include "gm20b/fuse_gm20b.h" | ||
32 | |||
33 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> | ||
34 | |||
35 | int gp10b_fuse_check_priv_security(struct gk20a *g) | ||
36 | { | ||
37 | u32 gcplex_config; | ||
38 | |||
39 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | ||
40 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
41 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
42 | nvgpu_log(g, gpu_dbg_info, "priv sec is disabled in fmodel"); | ||
43 | return 0; | ||
44 | } | ||
45 | |||
46 | if (nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &gcplex_config)) { | ||
47 | nvgpu_err(g, "err reading gcplex config fuse, check fuse clk"); | ||
48 | return -EINVAL; | ||
49 | } | ||
50 | |||
51 | if (gk20a_readl(g, fuse_opt_priv_sec_en_r())) { | ||
52 | /* | ||
53 | * all falcons have to boot in LS mode and this needs | ||
54 | * wpr_enabled set to 1 and vpr_auto_fetch_disable | ||
55 | * set to 0. In this case gmmu tries to pull wpr | ||
56 | * and vpr settings from tegra mc | ||
57 | */ | ||
58 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
59 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | ||
60 | if ((gcplex_config & | ||
61 | GCPLEX_CONFIG_WPR_ENABLED_MASK) && | ||
62 | !(gcplex_config & | ||
63 | GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK)) { | ||
64 | if (gk20a_readl(g, fuse_opt_sec_debug_en_r())) | ||
65 | nvgpu_log(g, gpu_dbg_info, | ||
66 | "gcplex_config = 0x%08x, " | ||
67 | "secure mode: ACR debug", | ||
68 | gcplex_config); | ||
69 | else | ||
70 | nvgpu_log(g, gpu_dbg_info, | ||
71 | "gcplex_config = 0x%08x, " | ||
72 | "secure mode: ACR non debug", | ||
73 | gcplex_config); | ||
74 | |||
75 | } else { | ||
76 | nvgpu_err(g, "gcplex_config = 0x%08x " | ||
77 | "invalid wpr_enabled/vpr_auto_fetch_disable " | ||
78 | "with priv_sec_en", gcplex_config); | ||
79 | /* do not try to boot GPU */ | ||
80 | return -EINVAL; | ||
81 | } | ||
82 | } else { | ||
83 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
84 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
85 | nvgpu_log(g, gpu_dbg_info, | ||
86 | "gcplex_config = 0x%08x, non secure mode", | ||
87 | gcplex_config); | ||
88 | } | ||
89 | |||
90 | return 0; | ||
91 | } | ||