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path: root/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/fifo_gp10b.c')
-rw-r--r--drivers/gpu/nvgpu/gp10b/fifo_gp10b.c61
1 files changed, 27 insertions, 34 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
index 9cb26d3f..4766e0e4 100644
--- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
@@ -25,24 +25,24 @@
25#include "hw_ram_gp10b.h" 25#include "hw_ram_gp10b.h"
26 26
27static void gp10b_set_pdb_fault_replay_flags(struct gk20a *g, 27static void gp10b_set_pdb_fault_replay_flags(struct gk20a *g,
28 void *inst_ptr) 28 struct mem_desc *mem)
29{ 29{
30 u32 val; 30 u32 val;
31 31
32 gk20a_dbg_fn(""); 32 gk20a_dbg_fn("");
33 33
34 val = gk20a_mem_rd32(inst_ptr, 34 val = gk20a_mem_rd32(g, mem,
35 ram_in_page_dir_base_fault_replay_tex_w()); 35 ram_in_page_dir_base_fault_replay_tex_w());
36 val &= ~ram_in_page_dir_base_fault_replay_tex_m(); 36 val &= ~ram_in_page_dir_base_fault_replay_tex_m();
37 val |= ram_in_page_dir_base_fault_replay_tex_true_f(); 37 val |= ram_in_page_dir_base_fault_replay_tex_true_f();
38 gk20a_mem_wr32(inst_ptr, 38 gk20a_mem_wr32(g, mem,
39 ram_in_page_dir_base_fault_replay_tex_w(), val); 39 ram_in_page_dir_base_fault_replay_tex_w(), val);
40 40
41 val = gk20a_mem_rd32(inst_ptr, 41 val = gk20a_mem_rd32(g, mem,
42 ram_in_page_dir_base_fault_replay_gcc_w()); 42 ram_in_page_dir_base_fault_replay_gcc_w());
43 val &= ~ram_in_page_dir_base_fault_replay_gcc_m(); 43 val &= ~ram_in_page_dir_base_fault_replay_gcc_m();
44 val |= ram_in_page_dir_base_fault_replay_gcc_true_f(); 44 val |= ram_in_page_dir_base_fault_replay_gcc_true_f();
45 gk20a_mem_wr32(inst_ptr, 45 gk20a_mem_wr32(g, mem,
46 ram_in_page_dir_base_fault_replay_gcc_w(), val); 46 ram_in_page_dir_base_fault_replay_gcc_w(), val);
47 47
48 gk20a_dbg_fn("done"); 48 gk20a_dbg_fn("done");
@@ -52,28 +52,25 @@ static int channel_gp10b_commit_userd(struct channel_gk20a *c)
52{ 52{
53 u32 addr_lo; 53 u32 addr_lo;
54 u32 addr_hi; 54 u32 addr_hi;
55 void *inst_ptr;
56 struct gk20a *g = c->g; 55 struct gk20a *g = c->g;
57 56
58 gk20a_dbg_fn(""); 57 gk20a_dbg_fn("");
59 58
60 inst_ptr = c->inst_block.cpu_va;
61 if (!inst_ptr)
62 return -ENOMEM;
63
64 addr_lo = u64_lo32(c->userd_iova >> ram_userd_base_shift_v()); 59 addr_lo = u64_lo32(c->userd_iova >> ram_userd_base_shift_v());
65 addr_hi = u64_hi32(c->userd_iova); 60 addr_hi = u64_hi32(c->userd_iova);
66 61
67 gk20a_dbg_info("channel %d : set ramfc userd 0x%16llx", 62 gk20a_dbg_info("channel %d : set ramfc userd 0x%16llx",
68 c->hw_chid, (u64)c->userd_iova); 63 c->hw_chid, (u64)c->userd_iova);
69 64
70 gk20a_mem_wr32(inst_ptr, ram_in_ramfc_w() + ram_fc_userd_w(), 65 gk20a_mem_wr32(g, &c->inst_block,
66 ram_in_ramfc_w() + ram_fc_userd_w(),
71 (g->mm.vidmem_is_vidmem ? 67 (g->mm.vidmem_is_vidmem ?
72 pbdma_userd_target_sys_mem_ncoh_f() : 68 pbdma_userd_target_sys_mem_ncoh_f() :
73 pbdma_userd_target_vid_mem_f()) | 69 pbdma_userd_target_vid_mem_f()) |
74 pbdma_userd_addr_f(addr_lo)); 70 pbdma_userd_addr_f(addr_lo));
75 71
76 gk20a_mem_wr32(inst_ptr, ram_in_ramfc_w() + ram_fc_userd_hi_w(), 72 gk20a_mem_wr32(g, &c->inst_block,
73 ram_in_ramfc_w() + ram_fc_userd_hi_w(),
77 pbdma_userd_hi_addr_f(addr_hi)); 74 pbdma_userd_hi_addr_f(addr_hi));
78 75
79 return 0; 76 return 0;
@@ -82,33 +79,30 @@ static int channel_gp10b_commit_userd(struct channel_gk20a *c)
82static int channel_gp10b_setup_ramfc(struct channel_gk20a *c, 79static int channel_gp10b_setup_ramfc(struct channel_gk20a *c,
83 u64 gpfifo_base, u32 gpfifo_entries, u32 flags) 80 u64 gpfifo_base, u32 gpfifo_entries, u32 flags)
84{ 81{
85 void *inst_ptr; 82 struct gk20a *g = c->g;
83 struct mem_desc *mem = &c->inst_block;
86 84
87 gk20a_dbg_fn(""); 85 gk20a_dbg_fn("");
88 86
89 inst_ptr = c->inst_block.cpu_va; 87 gk20a_memset(g, mem, 0, 0, ram_fc_size_val_v());
90 if (!inst_ptr)
91 return -ENOMEM;
92 88
93 memset(inst_ptr, 0, ram_fc_size_val_v()); 89 gk20a_mem_wr32(g, mem, ram_fc_gp_base_w(),
94
95 gk20a_mem_wr32(inst_ptr, ram_fc_gp_base_w(),
96 pbdma_gp_base_offset_f( 90 pbdma_gp_base_offset_f(
97 u64_lo32(gpfifo_base >> pbdma_gp_base_rsvd_s()))); 91 u64_lo32(gpfifo_base >> pbdma_gp_base_rsvd_s())));
98 92
99 gk20a_mem_wr32(inst_ptr, ram_fc_gp_base_hi_w(), 93 gk20a_mem_wr32(g, mem, ram_fc_gp_base_hi_w(),
100 pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) | 94 pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) |
101 pbdma_gp_base_hi_limit2_f(ilog2(gpfifo_entries))); 95 pbdma_gp_base_hi_limit2_f(ilog2(gpfifo_entries)));
102 96
103 gk20a_mem_wr32(inst_ptr, ram_fc_signature_w(), 97 gk20a_mem_wr32(g, mem, ram_fc_signature_w(),
104 c->g->ops.fifo.get_pbdma_signature(c->g)); 98 c->g->ops.fifo.get_pbdma_signature(c->g));
105 99
106 gk20a_mem_wr32(inst_ptr, ram_fc_formats_w(), 100 gk20a_mem_wr32(g, mem, ram_fc_formats_w(),
107 pbdma_formats_gp_fermi0_f() | 101 pbdma_formats_gp_fermi0_f() |
108 pbdma_formats_pb_fermi1_f() | 102 pbdma_formats_pb_fermi1_f() |
109 pbdma_formats_mp_fermi0_f()); 103 pbdma_formats_mp_fermi0_f());
110 104
111 gk20a_mem_wr32(inst_ptr, ram_fc_pb_header_w(), 105 gk20a_mem_wr32(g, mem, ram_fc_pb_header_w(),
112 pbdma_pb_header_priv_user_f() | 106 pbdma_pb_header_priv_user_f() |
113 pbdma_pb_header_method_zero_f() | 107 pbdma_pb_header_method_zero_f() |
114 pbdma_pb_header_subchannel_zero_f() | 108 pbdma_pb_header_subchannel_zero_f() |
@@ -116,26 +110,26 @@ static int channel_gp10b_setup_ramfc(struct channel_gk20a *c,
116 pbdma_pb_header_first_true_f() | 110 pbdma_pb_header_first_true_f() |
117 pbdma_pb_header_type_inc_f()); 111 pbdma_pb_header_type_inc_f());
118 112
119 gk20a_mem_wr32(inst_ptr, ram_fc_subdevice_w(), 113 gk20a_mem_wr32(g, mem, ram_fc_subdevice_w(),
120 pbdma_subdevice_id_f(1) | 114 pbdma_subdevice_id_f(1) |
121 pbdma_subdevice_status_active_f() | 115 pbdma_subdevice_status_active_f() |
122 pbdma_subdevice_channel_dma_enable_f()); 116 pbdma_subdevice_channel_dma_enable_f());
123 117
124 gk20a_mem_wr32(inst_ptr, ram_fc_target_w(), pbdma_target_engine_sw_f()); 118 gk20a_mem_wr32(g, mem, ram_fc_target_w(), pbdma_target_engine_sw_f());
125 119
126 gk20a_mem_wr32(inst_ptr, ram_fc_acquire_w(), 120 gk20a_mem_wr32(g, mem, ram_fc_acquire_w(),
127 channel_gk20a_pbdma_acquire_val(c)); 121 channel_gk20a_pbdma_acquire_val(c));
128 122
129 gk20a_mem_wr32(inst_ptr, ram_fc_runlist_timeslice_w(), 123 gk20a_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(),
130 pbdma_runlist_timeslice_timeout_128_f() | 124 pbdma_runlist_timeslice_timeout_128_f() |
131 pbdma_runlist_timeslice_timescale_3_f() | 125 pbdma_runlist_timeslice_timescale_3_f() |
132 pbdma_runlist_timeslice_enable_true_f()); 126 pbdma_runlist_timeslice_enable_true_f());
133 127
134 if ( flags & NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE) 128 if ( flags & NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE)
135 gp10b_set_pdb_fault_replay_flags(c->g, inst_ptr); 129 gp10b_set_pdb_fault_replay_flags(c->g, mem);
136 130
137 131
138 gk20a_mem_wr32(inst_ptr, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid)); 132 gk20a_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid));
139 133
140 return channel_gp10b_commit_userd(c); 134 return channel_gp10b_commit_userd(c);
141} 135}
@@ -149,14 +143,12 @@ static u32 gp10b_fifo_get_pbdma_signature(struct gk20a *g)
149static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c) 143static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c)
150{ 144{
151 u32 new_syncpt = 0, old_syncpt; 145 u32 new_syncpt = 0, old_syncpt;
152 void *inst_ptr;
153 u32 v; 146 u32 v;
154 147
155 gk20a_dbg_fn(""); 148 gk20a_dbg_fn("");
156 149
157 inst_ptr = c->inst_block.cpu_va; 150 v = gk20a_mem_rd32(c->g, &c->inst_block,
158 151 ram_fc_allowed_syncpoints_w());
159 v = gk20a_mem_rd32(inst_ptr, ram_fc_allowed_syncpoints_w());
160 old_syncpt = pbdma_allowed_syncpoints_0_index_v(v); 152 old_syncpt = pbdma_allowed_syncpoints_0_index_v(v);
161 if (c->sync) 153 if (c->sync)
162 new_syncpt = c->sync->syncpt_id(c->sync); 154 new_syncpt = c->sync->syncpt_id(c->sync);
@@ -175,7 +167,8 @@ static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c)
175 167
176 v |= pbdma_allowed_syncpoints_0_index_f(new_syncpt); 168 v |= pbdma_allowed_syncpoints_0_index_f(new_syncpt);
177 169
178 gk20a_mem_wr32(inst_ptr, ram_fc_allowed_syncpoints_w(), v); 170 gk20a_mem_wr32(c->g, &c->inst_block,
171 ram_fc_allowed_syncpoints_w(), v);
179 } 172 }
180 173
181 /* enable channel */ 174 /* enable channel */