diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/ce_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/ce_gp10b.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c index 86a2b751..e2ad1bd3 100644 --- a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Pascal GPU series Copy Engine. | 2 | * Pascal GPU series Copy Engine. |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -30,14 +30,14 @@ | |||
30 | 30 | ||
31 | static u32 ce_blockpipe_isr(struct gk20a *g, u32 fifo_intr) | 31 | static u32 ce_blockpipe_isr(struct gk20a *g, u32 fifo_intr) |
32 | { | 32 | { |
33 | gk20a_dbg(gpu_dbg_intr, "ce blocking pipe interrupt\n"); | 33 | nvgpu_log(g, gpu_dbg_intr, "ce blocking pipe interrupt\n"); |
34 | 34 | ||
35 | return ce_intr_status_blockpipe_pending_f(); | 35 | return ce_intr_status_blockpipe_pending_f(); |
36 | } | 36 | } |
37 | 37 | ||
38 | static u32 ce_launcherr_isr(struct gk20a *g, u32 fifo_intr) | 38 | static u32 ce_launcherr_isr(struct gk20a *g, u32 fifo_intr) |
39 | { | 39 | { |
40 | gk20a_dbg(gpu_dbg_intr, "ce launch error interrupt\n"); | 40 | nvgpu_log(g, gpu_dbg_intr, "ce launch error interrupt\n"); |
41 | 41 | ||
42 | return ce_intr_status_launcherr_pending_f(); | 42 | return ce_intr_status_launcherr_pending_f(); |
43 | } | 43 | } |
@@ -47,7 +47,7 @@ void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | |||
47 | u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); | 47 | u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); |
48 | u32 clear_intr = 0; | 48 | u32 clear_intr = 0; |
49 | 49 | ||
50 | gk20a_dbg(gpu_dbg_intr, "ce isr %08x %08x\n", ce_intr, inst_id); | 50 | nvgpu_log(g, gpu_dbg_intr, "ce isr %08x %08x\n", ce_intr, inst_id); |
51 | 51 | ||
52 | /* clear blocking interrupts: they exibit broken behavior */ | 52 | /* clear blocking interrupts: they exibit broken behavior */ |
53 | if (ce_intr & ce_intr_status_blockpipe_pending_f()) | 53 | if (ce_intr & ce_intr_status_blockpipe_pending_f()) |
@@ -65,7 +65,7 @@ int gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | |||
65 | int ops = 0; | 65 | int ops = 0; |
66 | u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); | 66 | u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); |
67 | 67 | ||
68 | gk20a_dbg(gpu_dbg_intr, "ce nonstall isr %08x %08x\n", ce_intr, inst_id); | 68 | nvgpu_log(g, gpu_dbg_intr, "ce nonstall isr %08x %08x\n", ce_intr, inst_id); |
69 | 69 | ||
70 | if (ce_intr & ce_intr_status_nonblockpipe_pending_f()) { | 70 | if (ce_intr & ce_intr_status_nonblockpipe_pending_f()) { |
71 | gk20a_writel(g, ce_intr_status_r(inst_id), | 71 | gk20a_writel(g, ce_intr_status_r(inst_id), |