diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/ce_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/ce_gp10b.c | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c new file mode 100644 index 00000000..e5082778 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c | |||
@@ -0,0 +1,82 @@ | |||
1 | /* | ||
2 | * Pascal GPU series Copy Engine. | ||
3 | * | ||
4 | * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License along with | ||
16 | * this program. | ||
17 | */ | ||
18 | |||
19 | #include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */ | ||
20 | #include "hw_ce_gp10b.h" | ||
21 | #include "ce_gp10b.h" | ||
22 | |||
23 | static void ce_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr) | ||
24 | { | ||
25 | gk20a_dbg(gpu_dbg_intr, "ce non-blocking pipe interrupt\n"); | ||
26 | |||
27 | /* wake theads waiting in this channel */ | ||
28 | gk20a_channel_semaphore_wakeup(g, true); | ||
29 | return; | ||
30 | } | ||
31 | |||
32 | static u32 ce_blockpipe_isr(struct gk20a *g, u32 fifo_intr) | ||
33 | { | ||
34 | gk20a_dbg(gpu_dbg_intr, "ce blocking pipe interrupt\n"); | ||
35 | |||
36 | return ce_intr_status_blockpipe_pending_f(); | ||
37 | } | ||
38 | |||
39 | static u32 ce_launcherr_isr(struct gk20a *g, u32 fifo_intr) | ||
40 | { | ||
41 | gk20a_dbg(gpu_dbg_intr, "ce launch error interrupt\n"); | ||
42 | |||
43 | return ce_intr_status_launcherr_pending_f(); | ||
44 | } | ||
45 | |||
46 | static void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | ||
47 | { | ||
48 | u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); | ||
49 | u32 clear_intr = 0; | ||
50 | |||
51 | gk20a_dbg(gpu_dbg_intr, "ce isr %08x %08x\n", ce_intr, inst_id); | ||
52 | |||
53 | /* clear blocking interrupts: they exibit broken behavior */ | ||
54 | if (ce_intr & ce_intr_status_blockpipe_pending_f()) | ||
55 | clear_intr |= ce_blockpipe_isr(g, ce_intr); | ||
56 | |||
57 | if (ce_intr & ce_intr_status_launcherr_pending_f()) | ||
58 | clear_intr |= ce_launcherr_isr(g, ce_intr); | ||
59 | |||
60 | gk20a_writel(g, ce_intr_status_r(inst_id), clear_intr); | ||
61 | return; | ||
62 | } | ||
63 | |||
64 | static void gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | ||
65 | { | ||
66 | u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); | ||
67 | |||
68 | gk20a_dbg(gpu_dbg_intr, "ce nonstall isr %08x %08x\n", ce_intr, inst_id); | ||
69 | |||
70 | if (ce_intr & ce_intr_status_nonblockpipe_pending_f()) { | ||
71 | gk20a_writel(g, ce_intr_status_r(inst_id), | ||
72 | ce_intr_status_nonblockpipe_pending_f()); | ||
73 | ce_nonblockpipe_isr(g, ce_intr); | ||
74 | } | ||
75 | |||
76 | return; | ||
77 | } | ||
78 | void gp10b_init_ce(struct gpu_ops *gops) | ||
79 | { | ||
80 | gops->ce2.isr_stall = gp10b_ce_isr; | ||
81 | gops->ce2.isr_nonstall = gp10b_ce_nonstall_isr; | ||
82 | } | ||