diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/ce_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/ce_gp10b.c | 19 |
1 files changed, 6 insertions, 13 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c index f19a4b0f..169309fa 100644 --- a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Pascal GPU series Copy Engine. | 2 | * Pascal GPU series Copy Engine. |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -22,15 +22,6 @@ | |||
22 | 22 | ||
23 | #include <nvgpu/hw/gp10b/hw_ce_gp10b.h> | 23 | #include <nvgpu/hw/gp10b/hw_ce_gp10b.h> |
24 | 24 | ||
25 | static void ce_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr) | ||
26 | { | ||
27 | gk20a_dbg(gpu_dbg_intr, "ce non-blocking pipe interrupt\n"); | ||
28 | |||
29 | /* wake theads waiting in this channel */ | ||
30 | gk20a_channel_semaphore_wakeup(g, true); | ||
31 | return; | ||
32 | } | ||
33 | |||
34 | static u32 ce_blockpipe_isr(struct gk20a *g, u32 fifo_intr) | 25 | static u32 ce_blockpipe_isr(struct gk20a *g, u32 fifo_intr) |
35 | { | 26 | { |
36 | gk20a_dbg(gpu_dbg_intr, "ce blocking pipe interrupt\n"); | 27 | gk20a_dbg(gpu_dbg_intr, "ce blocking pipe interrupt\n"); |
@@ -63,8 +54,9 @@ static void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | |||
63 | return; | 54 | return; |
64 | } | 55 | } |
65 | 56 | ||
66 | static void gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | 57 | static int gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) |
67 | { | 58 | { |
59 | int ops = 0; | ||
68 | u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); | 60 | u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); |
69 | 61 | ||
70 | gk20a_dbg(gpu_dbg_intr, "ce nonstall isr %08x %08x\n", ce_intr, inst_id); | 62 | gk20a_dbg(gpu_dbg_intr, "ce nonstall isr %08x %08x\n", ce_intr, inst_id); |
@@ -72,10 +64,11 @@ static void gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | |||
72 | if (ce_intr & ce_intr_status_nonblockpipe_pending_f()) { | 64 | if (ce_intr & ce_intr_status_nonblockpipe_pending_f()) { |
73 | gk20a_writel(g, ce_intr_status_r(inst_id), | 65 | gk20a_writel(g, ce_intr_status_r(inst_id), |
74 | ce_intr_status_nonblockpipe_pending_f()); | 66 | ce_intr_status_nonblockpipe_pending_f()); |
75 | ce_nonblockpipe_isr(g, ce_intr); | 67 | ops |= (gk20a_nonstall_ops_wakeup_semaphore | |
68 | gk20a_nonstall_ops_post_events); | ||
76 | } | 69 | } |
77 | 70 | ||
78 | return; | 71 | return ops; |
79 | } | 72 | } |
80 | void gp10b_init_ce(struct gpu_ops *gops) | 73 | void gp10b_init_ce(struct gpu_ops *gops) |
81 | { | 74 | { |