diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp10b/ce2_gp10b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/ce2_gp10b.c | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c b/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c new file mode 100644 index 00000000..d76b97a5 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c | |||
@@ -0,0 +1,83 @@ | |||
1 | /* | ||
2 | * GK20A Graphics Copy Engine (gr host) | ||
3 | * | ||
4 | * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License along with | ||
16 | * this program; if not, write to the Free Software Foundation, Inc., | ||
17 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | ||
18 | */ | ||
19 | |||
20 | #include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */ | ||
21 | #include "hw_ce2_gp10b.h" | ||
22 | #include "ce2_gp10b.h" | ||
23 | |||
24 | static u32 ce2_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr) | ||
25 | { | ||
26 | gk20a_dbg(gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n"); | ||
27 | |||
28 | /* wake theads waiting in this channel */ | ||
29 | gk20a_channel_semaphore_wakeup(g); | ||
30 | return ce2_intr_status_nonblockpipe_pending_f(); | ||
31 | } | ||
32 | |||
33 | static u32 ce2_blockpipe_isr(struct gk20a *g, u32 fifo_intr) | ||
34 | { | ||
35 | gk20a_dbg(gpu_dbg_intr, "ce2 blocking pipe interrupt\n"); | ||
36 | |||
37 | return ce2_intr_status_blockpipe_pending_f(); | ||
38 | } | ||
39 | |||
40 | static u32 ce2_launcherr_isr(struct gk20a *g, u32 fifo_intr) | ||
41 | { | ||
42 | gk20a_dbg(gpu_dbg_intr, "ce2 launch error interrupt\n"); | ||
43 | |||
44 | return ce2_intr_status_launcherr_pending_f(); | ||
45 | } | ||
46 | |||
47 | void gp10b_ce2_isr(struct gk20a *g) | ||
48 | { | ||
49 | u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r(0)); | ||
50 | u32 clear_intr = 0; | ||
51 | |||
52 | gk20a_dbg(gpu_dbg_intr, "ce2 isr %08x\n", ce2_intr); | ||
53 | |||
54 | /* clear blocking interrupts: they exibit broken behavior */ | ||
55 | if (ce2_intr & ce2_intr_status_blockpipe_pending_f()) | ||
56 | clear_intr |= ce2_blockpipe_isr(g, ce2_intr); | ||
57 | |||
58 | if (ce2_intr & ce2_intr_status_launcherr_pending_f()) | ||
59 | clear_intr |= ce2_launcherr_isr(g, ce2_intr); | ||
60 | |||
61 | gk20a_writel(g, ce2_intr_status_r(0), clear_intr); | ||
62 | return; | ||
63 | } | ||
64 | |||
65 | void gp10b_ce2_nonstall_isr(struct gk20a *g) | ||
66 | { | ||
67 | u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r(0)); | ||
68 | u32 clear_intr = 0; | ||
69 | |||
70 | gk20a_dbg(gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr); | ||
71 | |||
72 | if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) | ||
73 | clear_intr |= ce2_nonblockpipe_isr(g, ce2_intr); | ||
74 | |||
75 | gk20a_writel(g, ce2_intr_status_r(0), clear_intr); | ||
76 | |||
77 | return; | ||
78 | } | ||
79 | void gp10b_init_ce2(struct gpu_ops *gops) | ||
80 | { | ||
81 | gops->ce2.isr_stall = gp10b_ce2_isr; | ||
82 | gops->ce2.isr_nonstall = gp10b_ce2_nonstall_isr; | ||
83 | } | ||