3 files changed, 6 insertions, 202 deletions

diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.c b/drivers/gpu/nvgpu/gp106/clk_gp106.c
index dd7a2dd6..13a401f0 100644
--- a/drivers/gpu/nvgpu/gp106/clk_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/clk_gp106.c
@@ -22,11 +22,6 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifdef CONFIG_DEBUG_FS
-#include <linux/debugfs.h>
-#include "os/linux/os_linux.h"
-#endif
-
 #include <nvgpu/kmem.h>
 #include <nvgpu/io.h>
 #include <nvgpu/list.h>
@@ -42,15 +37,9 @@
 
 #include <nvgpu/hw/gp106/hw_trim_gp106.h>
 
-#ifdef CONFIG_DEBUG_FS
-static int clk_gp106_debugfs_init(struct gk20a *g);
-#endif
-
 #define NUM_NAMEMAPS    4
 #define XTAL4X_KHZ 108000
 
-
-static u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *);
 u32 gp106_crystal_clk_hz(struct gk20a *g)
 {
         return (XTAL4X_KHZ * 1000);
@@ -173,16 +162,11 @@ int gp106_init_clk_support(struct gk20a *g)
 
         clk->g = g;
 
-#ifdef CONFIG_DEBUG_FS
-        if (!clk->debugfs_set) {
-                if (!clk_gp106_debugfs_init(g))
-                        clk->debugfs_set = true;
-        }
-#endif
         return err;
 }
 
-static u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) {
+u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c)
+{
         u32 save_reg;
         u32 retries;
         u32 cntr = 0;
@@ -275,174 +259,6 @@ int gp106_clk_domain_get_f_points(
         return status;
 }
 
-
-#ifdef CONFIG_DEBUG_FS
-static int gp106_get_rate_show(void *data , u64 *val) {
-        struct namemap_cfg *c = (struct namemap_cfg *) data;
-        struct gk20a *g = c->g;
-
-        *val = c->is_counter ? (u64)c->scale * gp106_get_rate_cntr(g, c) :
-                0 /* TODO PLL read */;
-        return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(get_rate_fops, gp106_get_rate_show, NULL, "%llu\n");
-
-static int sys_cfc_read(void *data , u64 *val)
-{
-        struct gk20a *g = (struct gk20a *)data;
-        bool bload = boardobjgrpmask_bitget(
-                &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super,
-                CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS);
-
-        /* val = 1 implies CLFC is loaded or enabled */
-        *val = bload ? 1 : 0;
-        return 0;
-}
-static int sys_cfc_write(void *data , u64 val)
-{
-        struct gk20a *g = (struct gk20a *)data;
-        int status;
-        /* val = 1 implies load or enable the CLFC */
-        bool bload = val ? true : false;
-
-        nvgpu_clk_arb_pstate_change_lock(g, true);
-        status = clk_pmu_freq_controller_load(g, bload,
-                                        CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS);
-        nvgpu_clk_arb_pstate_change_lock(g, false);
-
-        return status;
-}
-DEFINE_SIMPLE_ATTRIBUTE(sys_cfc_fops, sys_cfc_read, sys_cfc_write, "%llu\n");
-
-static int ltc_cfc_read(void *data , u64 *val)
-{
-        struct gk20a *g = (struct gk20a *)data;
-        bool bload = boardobjgrpmask_bitget(
-                &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super,
-                CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC);
-
-        /* val = 1 implies CLFC is loaded or enabled */
-        *val = bload ? 1 : 0;
-        return 0;
-}
-static int ltc_cfc_write(void *data , u64 val)
-{
-        struct gk20a *g = (struct gk20a *)data;
-        int status;
-        /* val = 1 implies load or enable the CLFC */
-        bool bload = val ? true : false;
-
-        nvgpu_clk_arb_pstate_change_lock(g, true);
-        status = clk_pmu_freq_controller_load(g, bload,
-                                        CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC);
-        nvgpu_clk_arb_pstate_change_lock(g, false);
-
-        return status;
-}
-DEFINE_SIMPLE_ATTRIBUTE(ltc_cfc_fops, ltc_cfc_read, ltc_cfc_write, "%llu\n");
-
-static int xbar_cfc_read(void *data , u64 *val)
-{
-        struct gk20a *g = (struct gk20a *)data;
-        bool bload = boardobjgrpmask_bitget(
-                &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super,
-                CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR);
-
-        /* val = 1 implies CLFC is loaded or enabled */
-        *val = bload ? 1 : 0;
-        return 0;
-}
-static int xbar_cfc_write(void *data , u64 val)
-{
-        struct gk20a *g = (struct gk20a *)data;
-        int status;
-        /* val = 1 implies load or enable the CLFC */
-        bool bload = val ? true : false;
-
-        nvgpu_clk_arb_pstate_change_lock(g, true);
-        status = clk_pmu_freq_controller_load(g, bload,
-                        CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR);
-        nvgpu_clk_arb_pstate_change_lock(g, false);
-
-        return status;
-}
-DEFINE_SIMPLE_ATTRIBUTE(xbar_cfc_fops, xbar_cfc_read,
-                        xbar_cfc_write, "%llu\n");
-
-static int gpc_cfc_read(void *data , u64 *val)
-{
-        struct gk20a *g = (struct gk20a *)data;
-        bool bload = boardobjgrpmask_bitget(
-                &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super,
-                CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0);
-
-        /* val = 1 implies CLFC is loaded or enabled */
-        *val = bload ? 1 : 0;
-        return 0;
-}
-static int gpc_cfc_write(void *data , u64 val)
-{
-        struct gk20a *g = (struct gk20a *)data;
-        int status;
-        /* val = 1 implies load or enable the CLFC */
-        bool bload = val ? true : false;
-
-        nvgpu_clk_arb_pstate_change_lock(g, true);
-        status = clk_pmu_freq_controller_load(g, bload,
-                        CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0);
-        nvgpu_clk_arb_pstate_change_lock(g, false);
-
-        return status;
-}
-DEFINE_SIMPLE_ATTRIBUTE(gpc_cfc_fops, gpc_cfc_read, gpc_cfc_write, "%llu\n");
-
-static int clk_gp106_debugfs_init(struct gk20a *g)
-{
-        struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
-        struct dentry *gpu_root = l->debugfs;
-        struct dentry *clocks_root, *clk_freq_ctlr_root;
-        struct dentry *d;
-        unsigned int i;
-
-        if (NULL == (clocks_root = debugfs_create_dir("clocks", gpu_root)))
-                return -ENOMEM;
-
-        clk_freq_ctlr_root = debugfs_create_dir("clk_freq_ctlr", gpu_root);
-        if (clk_freq_ctlr_root == NULL)
-                return -ENOMEM;
-
-        d = debugfs_create_file("sys", S_IRUGO | S_IWUSR, clk_freq_ctlr_root,
-                                g, &sys_cfc_fops);
-        d = debugfs_create_file("ltc", S_IRUGO | S_IWUSR, clk_freq_ctlr_root,
-                                g, &ltc_cfc_fops);
-        d = debugfs_create_file("xbar", S_IRUGO | S_IWUSR, clk_freq_ctlr_root,
-                                g, &xbar_cfc_fops);
-        d = debugfs_create_file("gpc", S_IRUGO | S_IWUSR, clk_freq_ctlr_root,
-                                g, &gpc_cfc_fops);
-
-        nvgpu_log(g, gpu_dbg_info, "g=%p", g);
-
-        for (i = 0; i < g->clk.namemap_num; i++) {
-                if (g->clk.clk_namemap[i].is_enable) {
-                        d = debugfs_create_file(
-                                g->clk.clk_namemap[i].name,
-                                S_IRUGO,
-                                clocks_root,
-                                &g->clk.clk_namemap[i],
-                                &get_rate_fops);
-                        if (!d)
-                                goto err_out;
-                }
-        }
-        return 0;
-
-err_out:
-        pr_err("%s: Failed to make debugfs node\n", __func__);
-        debugfs_remove_recursive(clocks_root);
-        return -ENOMEM;
-}
-#endif /* CONFIG_DEBUG_FS */
-
 int gp106_suspend_clk_support(struct gk20a *g)
 {
         nvgpu_mutex_destroy(&g->clk.clk_mutex);
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.h b/drivers/gpu/nvgpu/gp106/clk_gp106.h
index b7ab3164..079b94f0 100644
--- a/drivers/gpu/nvgpu/gp106/clk_gp106.h
+++ b/drivers/gpu/nvgpu/gp106/clk_gp106.h
@@ -23,6 +23,7 @@
 #define CLK_GP106_H
 
 #include <nvgpu/lock.h>
+#include <nvgpu/clk.h>
 
 #define CLK_NAMEMAP_INDEX_GPC2CLK       0x00
 #define CLK_NAMEMAP_INDEX_XBAR2CLK      0x02
@@ -36,22 +37,7 @@
 #define XTAL_CNTR_DELAY         1000    /* we need acuracy up to the ms   */
 #define XTAL_SCALE_TO_KHZ       1
 
-
-
-struct namemap_cfg {
-        u32 namemap;
-        u32 is_enable;  /* Namemap enabled */
-        u32 is_counter; /* Using cntr */
-        struct gk20a *g;
-        struct {
-                u32 reg_ctrl_addr;
-                u32 reg_ctrl_idx;
-                u32 reg_cntr_addr;
-        } cntr;
-        u32 scale;
-        char name[24];
-};
-
+u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c);
 int gp106_init_clk_support(struct gk20a *g);
 u32 gp106_crystal_clk_hz(struct gk20a *g);
 unsigned long gp106_clk_measure_freq(struct gk20a *g, u32 api_domain);
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index f1a701a0..af2d4c00 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -673,6 +673,7 @@ static const struct gpu_ops gp106_ops = {
         .clk = {
                 .init_clk_support = gp106_init_clk_support,
                 .get_crystal_clk_hz = gp106_crystal_clk_hz,
+                .get_rate_cntr = gp106_get_rate_cntr,
                 .measure_freq = gp106_clk_measure_freq,
                 .suspend_clk_support = gp106_suspend_clk_support,
                 .clk_domain_get_f_points = gp106_clk_domain_get_f_points,
@@ -848,6 +849,7 @@ int gp106_init_hal(struct gk20a *g)
          */
         gops->clk.init_clk_support = gp106_ops.clk.init_clk_support;
         gops->clk.get_crystal_clk_hz = gp106_ops.clk.get_crystal_clk_hz;
+        gops->clk.get_rate_cntr = gp106_ops.clk.get_rate_cntr;
         gops->clk.measure_freq = gp106_ops.clk.measure_freq;
         gops->clk.suspend_clk_support = gp106_ops.clk.suspend_clk_support;
         gops->clk.mclk_init = gp106_ops.clk.mclk_init;