diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp106')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/clk_gp106.c | 188 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/clk_gp106.h | 18 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 2 |
3 files changed, 6 insertions, 202 deletions
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.c b/drivers/gpu/nvgpu/gp106/clk_gp106.c index dd7a2dd6..13a401f0 100644 --- a/drivers/gpu/nvgpu/gp106/clk_gp106.c +++ b/drivers/gpu/nvgpu/gp106/clk_gp106.c | |||
@@ -22,11 +22,6 @@ | |||
22 | * DEALINGS IN THE SOFTWARE. | 22 | * DEALINGS IN THE SOFTWARE. |
23 | */ | 23 | */ |
24 | 24 | ||
25 | #ifdef CONFIG_DEBUG_FS | ||
26 | #include <linux/debugfs.h> | ||
27 | #include "os/linux/os_linux.h" | ||
28 | #endif | ||
29 | |||
30 | #include <nvgpu/kmem.h> | 25 | #include <nvgpu/kmem.h> |
31 | #include <nvgpu/io.h> | 26 | #include <nvgpu/io.h> |
32 | #include <nvgpu/list.h> | 27 | #include <nvgpu/list.h> |
@@ -42,15 +37,9 @@ | |||
42 | 37 | ||
43 | #include <nvgpu/hw/gp106/hw_trim_gp106.h> | 38 | #include <nvgpu/hw/gp106/hw_trim_gp106.h> |
44 | 39 | ||
45 | #ifdef CONFIG_DEBUG_FS | ||
46 | static int clk_gp106_debugfs_init(struct gk20a *g); | ||
47 | #endif | ||
48 | |||
49 | #define NUM_NAMEMAPS 4 | 40 | #define NUM_NAMEMAPS 4 |
50 | #define XTAL4X_KHZ 108000 | 41 | #define XTAL4X_KHZ 108000 |
51 | 42 | ||
52 | |||
53 | static u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *); | ||
54 | u32 gp106_crystal_clk_hz(struct gk20a *g) | 43 | u32 gp106_crystal_clk_hz(struct gk20a *g) |
55 | { | 44 | { |
56 | return (XTAL4X_KHZ * 1000); | 45 | return (XTAL4X_KHZ * 1000); |
@@ -173,16 +162,11 @@ int gp106_init_clk_support(struct gk20a *g) | |||
173 | 162 | ||
174 | clk->g = g; | 163 | clk->g = g; |
175 | 164 | ||
176 | #ifdef CONFIG_DEBUG_FS | ||
177 | if (!clk->debugfs_set) { | ||
178 | if (!clk_gp106_debugfs_init(g)) | ||
179 | clk->debugfs_set = true; | ||
180 | } | ||
181 | #endif | ||
182 | return err; | 165 | return err; |
183 | } | 166 | } |
184 | 167 | ||
185 | static u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) { | 168 | u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) |
169 | { | ||
186 | u32 save_reg; | 170 | u32 save_reg; |
187 | u32 retries; | 171 | u32 retries; |
188 | u32 cntr = 0; | 172 | u32 cntr = 0; |
@@ -275,174 +259,6 @@ int gp106_clk_domain_get_f_points( | |||
275 | return status; | 259 | return status; |
276 | } | 260 | } |
277 | 261 | ||
278 | |||
279 | #ifdef CONFIG_DEBUG_FS | ||
280 | static int gp106_get_rate_show(void *data , u64 *val) { | ||
281 | struct namemap_cfg *c = (struct namemap_cfg *) data; | ||
282 | struct gk20a *g = c->g; | ||
283 | |||
284 | *val = c->is_counter ? (u64)c->scale * gp106_get_rate_cntr(g, c) : | ||
285 | 0 /* TODO PLL read */; | ||
286 | return 0; | ||
287 | } | ||
288 | DEFINE_SIMPLE_ATTRIBUTE(get_rate_fops, gp106_get_rate_show, NULL, "%llu\n"); | ||
289 | |||
290 | static int sys_cfc_read(void *data , u64 *val) | ||
291 | { | ||
292 | struct gk20a *g = (struct gk20a *)data; | ||
293 | bool bload = boardobjgrpmask_bitget( | ||
294 | &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super, | ||
295 | CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS); | ||
296 | |||
297 | /* val = 1 implies CLFC is loaded or enabled */ | ||
298 | *val = bload ? 1 : 0; | ||
299 | return 0; | ||
300 | } | ||
301 | static int sys_cfc_write(void *data , u64 val) | ||
302 | { | ||
303 | struct gk20a *g = (struct gk20a *)data; | ||
304 | int status; | ||
305 | /* val = 1 implies load or enable the CLFC */ | ||
306 | bool bload = val ? true : false; | ||
307 | |||
308 | nvgpu_clk_arb_pstate_change_lock(g, true); | ||
309 | status = clk_pmu_freq_controller_load(g, bload, | ||
310 | CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS); | ||
311 | nvgpu_clk_arb_pstate_change_lock(g, false); | ||
312 | |||
313 | return status; | ||
314 | } | ||
315 | DEFINE_SIMPLE_ATTRIBUTE(sys_cfc_fops, sys_cfc_read, sys_cfc_write, "%llu\n"); | ||
316 | |||
317 | static int ltc_cfc_read(void *data , u64 *val) | ||
318 | { | ||
319 | struct gk20a *g = (struct gk20a *)data; | ||
320 | bool bload = boardobjgrpmask_bitget( | ||
321 | &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super, | ||
322 | CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC); | ||
323 | |||
324 | /* val = 1 implies CLFC is loaded or enabled */ | ||
325 | *val = bload ? 1 : 0; | ||
326 | return 0; | ||
327 | } | ||
328 | static int ltc_cfc_write(void *data , u64 val) | ||
329 | { | ||
330 | struct gk20a *g = (struct gk20a *)data; | ||
331 | int status; | ||
332 | /* val = 1 implies load or enable the CLFC */ | ||
333 | bool bload = val ? true : false; | ||
334 | |||
335 | nvgpu_clk_arb_pstate_change_lock(g, true); | ||
336 | status = clk_pmu_freq_controller_load(g, bload, | ||
337 | CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC); | ||
338 | nvgpu_clk_arb_pstate_change_lock(g, false); | ||
339 | |||
340 | return status; | ||
341 | } | ||
342 | DEFINE_SIMPLE_ATTRIBUTE(ltc_cfc_fops, ltc_cfc_read, ltc_cfc_write, "%llu\n"); | ||
343 | |||
344 | static int xbar_cfc_read(void *data , u64 *val) | ||
345 | { | ||
346 | struct gk20a *g = (struct gk20a *)data; | ||
347 | bool bload = boardobjgrpmask_bitget( | ||
348 | &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super, | ||
349 | CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR); | ||
350 | |||
351 | /* val = 1 implies CLFC is loaded or enabled */ | ||
352 | *val = bload ? 1 : 0; | ||
353 | return 0; | ||
354 | } | ||
355 | static int xbar_cfc_write(void *data , u64 val) | ||
356 | { | ||
357 | struct gk20a *g = (struct gk20a *)data; | ||
358 | int status; | ||
359 | /* val = 1 implies load or enable the CLFC */ | ||
360 | bool bload = val ? true : false; | ||
361 | |||
362 | nvgpu_clk_arb_pstate_change_lock(g, true); | ||
363 | status = clk_pmu_freq_controller_load(g, bload, | ||
364 | CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR); | ||
365 | nvgpu_clk_arb_pstate_change_lock(g, false); | ||
366 | |||
367 | return status; | ||
368 | } | ||
369 | DEFINE_SIMPLE_ATTRIBUTE(xbar_cfc_fops, xbar_cfc_read, | ||
370 | xbar_cfc_write, "%llu\n"); | ||
371 | |||
372 | static int gpc_cfc_read(void *data , u64 *val) | ||
373 | { | ||
374 | struct gk20a *g = (struct gk20a *)data; | ||
375 | bool bload = boardobjgrpmask_bitget( | ||
376 | &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super, | ||
377 | CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0); | ||
378 | |||
379 | /* val = 1 implies CLFC is loaded or enabled */ | ||
380 | *val = bload ? 1 : 0; | ||
381 | return 0; | ||
382 | } | ||
383 | static int gpc_cfc_write(void *data , u64 val) | ||
384 | { | ||
385 | struct gk20a *g = (struct gk20a *)data; | ||
386 | int status; | ||
387 | /* val = 1 implies load or enable the CLFC */ | ||
388 | bool bload = val ? true : false; | ||
389 | |||
390 | nvgpu_clk_arb_pstate_change_lock(g, true); | ||
391 | status = clk_pmu_freq_controller_load(g, bload, | ||
392 | CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0); | ||
393 | nvgpu_clk_arb_pstate_change_lock(g, false); | ||
394 | |||
395 | return status; | ||
396 | } | ||
397 | DEFINE_SIMPLE_ATTRIBUTE(gpc_cfc_fops, gpc_cfc_read, gpc_cfc_write, "%llu\n"); | ||
398 | |||
399 | static int clk_gp106_debugfs_init(struct gk20a *g) | ||
400 | { | ||
401 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | ||
402 | struct dentry *gpu_root = l->debugfs; | ||
403 | struct dentry *clocks_root, *clk_freq_ctlr_root; | ||
404 | struct dentry *d; | ||
405 | unsigned int i; | ||
406 | |||
407 | if (NULL == (clocks_root = debugfs_create_dir("clocks", gpu_root))) | ||
408 | return -ENOMEM; | ||
409 | |||
410 | clk_freq_ctlr_root = debugfs_create_dir("clk_freq_ctlr", gpu_root); | ||
411 | if (clk_freq_ctlr_root == NULL) | ||
412 | return -ENOMEM; | ||
413 | |||
414 | d = debugfs_create_file("sys", S_IRUGO | S_IWUSR, clk_freq_ctlr_root, | ||
415 | g, &sys_cfc_fops); | ||
416 | d = debugfs_create_file("ltc", S_IRUGO | S_IWUSR, clk_freq_ctlr_root, | ||
417 | g, <c_cfc_fops); | ||
418 | d = debugfs_create_file("xbar", S_IRUGO | S_IWUSR, clk_freq_ctlr_root, | ||
419 | g, &xbar_cfc_fops); | ||
420 | d = debugfs_create_file("gpc", S_IRUGO | S_IWUSR, clk_freq_ctlr_root, | ||
421 | g, &gpc_cfc_fops); | ||
422 | |||
423 | nvgpu_log(g, gpu_dbg_info, "g=%p", g); | ||
424 | |||
425 | for (i = 0; i < g->clk.namemap_num; i++) { | ||
426 | if (g->clk.clk_namemap[i].is_enable) { | ||
427 | d = debugfs_create_file( | ||
428 | g->clk.clk_namemap[i].name, | ||
429 | S_IRUGO, | ||
430 | clocks_root, | ||
431 | &g->clk.clk_namemap[i], | ||
432 | &get_rate_fops); | ||
433 | if (!d) | ||
434 | goto err_out; | ||
435 | } | ||
436 | } | ||
437 | return 0; | ||
438 | |||
439 | err_out: | ||
440 | pr_err("%s: Failed to make debugfs node\n", __func__); | ||
441 | debugfs_remove_recursive(clocks_root); | ||
442 | return -ENOMEM; | ||
443 | } | ||
444 | #endif /* CONFIG_DEBUG_FS */ | ||
445 | |||
446 | int gp106_suspend_clk_support(struct gk20a *g) | 262 | int gp106_suspend_clk_support(struct gk20a *g) |
447 | { | 263 | { |
448 | nvgpu_mutex_destroy(&g->clk.clk_mutex); | 264 | nvgpu_mutex_destroy(&g->clk.clk_mutex); |
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.h b/drivers/gpu/nvgpu/gp106/clk_gp106.h index b7ab3164..079b94f0 100644 --- a/drivers/gpu/nvgpu/gp106/clk_gp106.h +++ b/drivers/gpu/nvgpu/gp106/clk_gp106.h | |||
@@ -23,6 +23,7 @@ | |||
23 | #define CLK_GP106_H | 23 | #define CLK_GP106_H |
24 | 24 | ||
25 | #include <nvgpu/lock.h> | 25 | #include <nvgpu/lock.h> |
26 | #include <nvgpu/clk.h> | ||
26 | 27 | ||
27 | #define CLK_NAMEMAP_INDEX_GPC2CLK 0x00 | 28 | #define CLK_NAMEMAP_INDEX_GPC2CLK 0x00 |
28 | #define CLK_NAMEMAP_INDEX_XBAR2CLK 0x02 | 29 | #define CLK_NAMEMAP_INDEX_XBAR2CLK 0x02 |
@@ -36,22 +37,7 @@ | |||
36 | #define XTAL_CNTR_DELAY 1000 /* we need acuracy up to the ms */ | 37 | #define XTAL_CNTR_DELAY 1000 /* we need acuracy up to the ms */ |
37 | #define XTAL_SCALE_TO_KHZ 1 | 38 | #define XTAL_SCALE_TO_KHZ 1 |
38 | 39 | ||
39 | 40 | u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c); | |
40 | |||
41 | struct namemap_cfg { | ||
42 | u32 namemap; | ||
43 | u32 is_enable; /* Namemap enabled */ | ||
44 | u32 is_counter; /* Using cntr */ | ||
45 | struct gk20a *g; | ||
46 | struct { | ||
47 | u32 reg_ctrl_addr; | ||
48 | u32 reg_ctrl_idx; | ||
49 | u32 reg_cntr_addr; | ||
50 | } cntr; | ||
51 | u32 scale; | ||
52 | char name[24]; | ||
53 | }; | ||
54 | |||
55 | int gp106_init_clk_support(struct gk20a *g); | 41 | int gp106_init_clk_support(struct gk20a *g); |
56 | u32 gp106_crystal_clk_hz(struct gk20a *g); | 42 | u32 gp106_crystal_clk_hz(struct gk20a *g); |
57 | unsigned long gp106_clk_measure_freq(struct gk20a *g, u32 api_domain); | 43 | unsigned long gp106_clk_measure_freq(struct gk20a *g, u32 api_domain); |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index f1a701a0..af2d4c00 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -673,6 +673,7 @@ static const struct gpu_ops gp106_ops = { | |||
673 | .clk = { | 673 | .clk = { |
674 | .init_clk_support = gp106_init_clk_support, | 674 | .init_clk_support = gp106_init_clk_support, |
675 | .get_crystal_clk_hz = gp106_crystal_clk_hz, | 675 | .get_crystal_clk_hz = gp106_crystal_clk_hz, |
676 | .get_rate_cntr = gp106_get_rate_cntr, | ||
676 | .measure_freq = gp106_clk_measure_freq, | 677 | .measure_freq = gp106_clk_measure_freq, |
677 | .suspend_clk_support = gp106_suspend_clk_support, | 678 | .suspend_clk_support = gp106_suspend_clk_support, |
678 | .clk_domain_get_f_points = gp106_clk_domain_get_f_points, | 679 | .clk_domain_get_f_points = gp106_clk_domain_get_f_points, |
@@ -848,6 +849,7 @@ int gp106_init_hal(struct gk20a *g) | |||
848 | */ | 849 | */ |
849 | gops->clk.init_clk_support = gp106_ops.clk.init_clk_support; | 850 | gops->clk.init_clk_support = gp106_ops.clk.init_clk_support; |
850 | gops->clk.get_crystal_clk_hz = gp106_ops.clk.get_crystal_clk_hz; | 851 | gops->clk.get_crystal_clk_hz = gp106_ops.clk.get_crystal_clk_hz; |
852 | gops->clk.get_rate_cntr = gp106_ops.clk.get_rate_cntr; | ||
851 | gops->clk.measure_freq = gp106_ops.clk.measure_freq; | 853 | gops->clk.measure_freq = gp106_ops.clk.measure_freq; |
852 | gops->clk.suspend_clk_support = gp106_ops.clk.suspend_clk_support; | 854 | gops->clk.suspend_clk_support = gp106_ops.clk.suspend_clk_support; |
853 | gops->clk.mclk_init = gp106_ops.clk.mclk_init; | 855 | gops->clk.mclk_init = gp106_ops.clk.mclk_init; |