2 files changed, 4 insertions, 4 deletions

diff --git a/drivers/gpu/nvgpu/gp106/mclk_gp106.c b/drivers/gpu/nvgpu/gp106/mclk_gp106.c
index c4ecdb1d..283847a9 100644
--- a/drivers/gpu/nvgpu/gp106/mclk_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/mclk_gp106.c
@@ -3371,7 +3371,7 @@ int gp106_mclk_change(struct gk20a *g, u16 val)
                         reg_alloc);
 
         /* Send command to PMU to execute sequencer script */
-        status = gk20a_pmu_cmd_post(g, (struct pmu_cmd *)&cmd, NULL, &payload,
+        status = nvgpu_pmu_cmd_post(g, (struct pmu_cmd *)&cmd, NULL, &payload,
                         PMU_COMMAND_QUEUE_LPQ,
                         mclk_seq_pmucmdhandler,
                         &seq_completion_status, &seqdesc, ~0);
diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_gp106.c
index eec89695..a09aa30b 100644
--- a/drivers/gpu/nvgpu/gp106/pmu_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.c
@@ -126,7 +126,7 @@ static int gp106_pg_param_init(struct gk20a *g, u32 pg_engine_id)
                                 PMU_PG_FEATURE_GR_RPPG_ENABLED;
 
                 gp106_dbg_pmu("cmd post GR PMU_PG_CMD_ID_PG_PARAM");
-                gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
+                nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
                                 pmu_handle_param_msg, pmu, &seq, ~0);
         } else if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS) {
                 cmd.hdr.unit_id = PMU_UNIT_PG;
@@ -143,7 +143,7 @@ static int gp106_pg_param_init(struct gk20a *g, u32 pg_engine_id)
                         NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING;
 
                 gp106_dbg_pmu("cmd post MS PMU_PG_CMD_ID_PG_PARAM");
-                gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
+                nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
                         pmu_handle_param_msg, pmu, &seq, ~0);
         }
 
@@ -250,7 +250,7 @@ static void gp106_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask,
 
                 gp106_dbg_pmu("PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS:%x\n",
                                 falconidmask);
-                gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
+                nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
                                 pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0);
         }