diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp106')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/clk_gp106.c | 123 |
1 files changed, 122 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.c b/drivers/gpu/nvgpu/gp106/clk_gp106.c index a7448cad..4b941433 100644 --- a/drivers/gpu/nvgpu/gp106/clk_gp106.c +++ b/drivers/gpu/nvgpu/gp106/clk_gp106.c | |||
@@ -242,18 +242,139 @@ static int gp106_get_rate_show(void *data , u64 *val) { | |||
242 | } | 242 | } |
243 | DEFINE_SIMPLE_ATTRIBUTE(get_rate_fops, gp106_get_rate_show, NULL, "%llu\n"); | 243 | DEFINE_SIMPLE_ATTRIBUTE(get_rate_fops, gp106_get_rate_show, NULL, "%llu\n"); |
244 | 244 | ||
245 | static int sys_cfc_read(void *data , u64 *val) | ||
246 | { | ||
247 | struct gk20a *g = (struct gk20a *)data; | ||
248 | bool bload = boardobjgrpmask_bitget( | ||
249 | &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super, | ||
250 | CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS); | ||
251 | |||
252 | /* val = 1 implies CLFC is loaded or enabled */ | ||
253 | *val = bload ? 1 : 0; | ||
254 | return 0; | ||
255 | } | ||
256 | static int sys_cfc_write(void *data , u64 val) | ||
257 | { | ||
258 | struct gk20a *g = (struct gk20a *)data; | ||
259 | int status; | ||
260 | /* val = 1 implies load or enable the CLFC */ | ||
261 | bool bload = val ? true : false; | ||
262 | |||
263 | nvgpu_clk_arb_pstate_change_lock(g, true); | ||
264 | status = clk_pmu_freq_controller_load(g, bload, | ||
265 | CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS); | ||
266 | nvgpu_clk_arb_pstate_change_lock(g, false); | ||
267 | |||
268 | return status; | ||
269 | } | ||
270 | DEFINE_SIMPLE_ATTRIBUTE(sys_cfc_fops, sys_cfc_read, sys_cfc_write, "%llu\n"); | ||
271 | |||
272 | static int ltc_cfc_read(void *data , u64 *val) | ||
273 | { | ||
274 | struct gk20a *g = (struct gk20a *)data; | ||
275 | bool bload = boardobjgrpmask_bitget( | ||
276 | &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super, | ||
277 | CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC); | ||
278 | |||
279 | /* val = 1 implies CLFC is loaded or enabled */ | ||
280 | *val = bload ? 1 : 0; | ||
281 | return 0; | ||
282 | } | ||
283 | static int ltc_cfc_write(void *data , u64 val) | ||
284 | { | ||
285 | struct gk20a *g = (struct gk20a *)data; | ||
286 | int status; | ||
287 | /* val = 1 implies load or enable the CLFC */ | ||
288 | bool bload = val ? true : false; | ||
289 | |||
290 | nvgpu_clk_arb_pstate_change_lock(g, true); | ||
291 | status = clk_pmu_freq_controller_load(g, bload, | ||
292 | CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC); | ||
293 | nvgpu_clk_arb_pstate_change_lock(g, false); | ||
294 | |||
295 | return status; | ||
296 | } | ||
297 | DEFINE_SIMPLE_ATTRIBUTE(ltc_cfc_fops, ltc_cfc_read, ltc_cfc_write, "%llu\n"); | ||
298 | |||
299 | static int xbar_cfc_read(void *data , u64 *val) | ||
300 | { | ||
301 | struct gk20a *g = (struct gk20a *)data; | ||
302 | bool bload = boardobjgrpmask_bitget( | ||
303 | &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super, | ||
304 | CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR); | ||
305 | |||
306 | /* val = 1 implies CLFC is loaded or enabled */ | ||
307 | *val = bload ? 1 : 0; | ||
308 | return 0; | ||
309 | } | ||
310 | static int xbar_cfc_write(void *data , u64 val) | ||
311 | { | ||
312 | struct gk20a *g = (struct gk20a *)data; | ||
313 | int status; | ||
314 | /* val = 1 implies load or enable the CLFC */ | ||
315 | bool bload = val ? true : false; | ||
316 | |||
317 | nvgpu_clk_arb_pstate_change_lock(g, true); | ||
318 | status = clk_pmu_freq_controller_load(g, bload, | ||
319 | CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR); | ||
320 | nvgpu_clk_arb_pstate_change_lock(g, false); | ||
321 | |||
322 | return status; | ||
323 | } | ||
324 | DEFINE_SIMPLE_ATTRIBUTE(xbar_cfc_fops, xbar_cfc_read, | ||
325 | xbar_cfc_write, "%llu\n"); | ||
326 | |||
327 | static int gpc_cfc_read(void *data , u64 *val) | ||
328 | { | ||
329 | struct gk20a *g = (struct gk20a *)data; | ||
330 | bool bload = boardobjgrpmask_bitget( | ||
331 | &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super, | ||
332 | CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0); | ||
333 | |||
334 | /* val = 1 implies CLFC is loaded or enabled */ | ||
335 | *val = bload ? 1 : 0; | ||
336 | return 0; | ||
337 | } | ||
338 | static int gpc_cfc_write(void *data , u64 val) | ||
339 | { | ||
340 | struct gk20a *g = (struct gk20a *)data; | ||
341 | int status; | ||
342 | /* val = 1 implies load or enable the CLFC */ | ||
343 | bool bload = val ? true : false; | ||
344 | |||
345 | nvgpu_clk_arb_pstate_change_lock(g, true); | ||
346 | status = clk_pmu_freq_controller_load(g, bload, | ||
347 | CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0); | ||
348 | nvgpu_clk_arb_pstate_change_lock(g, false); | ||
349 | |||
350 | return status; | ||
351 | } | ||
352 | DEFINE_SIMPLE_ATTRIBUTE(gpc_cfc_fops, gpc_cfc_read, gpc_cfc_write, "%llu\n"); | ||
245 | 353 | ||
246 | static int clk_gp106_debugfs_init(struct gk20a *g) | 354 | static int clk_gp106_debugfs_init(struct gk20a *g) |
247 | { | 355 | { |
248 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | 356 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); |
249 | struct dentry *gpu_root = l->debugfs; | 357 | struct dentry *gpu_root = l->debugfs; |
250 | struct dentry *clocks_root; | 358 | struct dentry *clocks_root, *clk_freq_ctlr_root; |
251 | struct dentry *d; | 359 | struct dentry *d; |
252 | unsigned int i; | 360 | unsigned int i; |
253 | 361 | ||
254 | if (NULL == (clocks_root = debugfs_create_dir("clocks", gpu_root))) | 362 | if (NULL == (clocks_root = debugfs_create_dir("clocks", gpu_root))) |
255 | return -ENOMEM; | 363 | return -ENOMEM; |
256 | 364 | ||
365 | clk_freq_ctlr_root = debugfs_create_dir("clk_freq_ctlr", gpu_root); | ||
366 | if (clk_freq_ctlr_root == NULL) | ||
367 | return -ENOMEM; | ||
368 | |||
369 | d = debugfs_create_file("sys", S_IRUGO | S_IWUSR, clk_freq_ctlr_root, | ||
370 | g, &sys_cfc_fops); | ||
371 | d = debugfs_create_file("ltc", S_IRUGO | S_IWUSR, clk_freq_ctlr_root, | ||
372 | g, <c_cfc_fops); | ||
373 | d = debugfs_create_file("xbar", S_IRUGO | S_IWUSR, clk_freq_ctlr_root, | ||
374 | g, &xbar_cfc_fops); | ||
375 | d = debugfs_create_file("gpc", S_IRUGO | S_IWUSR, clk_freq_ctlr_root, | ||
376 | g, &gpc_cfc_fops); | ||
377 | |||
257 | gk20a_dbg(gpu_dbg_info, "g=%p", g); | 378 | gk20a_dbg(gpu_dbg_info, "g=%p", g); |
258 | 379 | ||
259 | for (i = 0; i < g->clk.namemap_num; i++) { | 380 | for (i = 0; i < g->clk.namemap_num; i++) { |