diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp106')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/acr_gp106.c | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/pmu_gp106.c | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/sec2_gp106.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/sec2_gp106.h | 10 |
4 files changed, 27 insertions, 22 deletions
diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c index 5570489e..c7d71ab0 100644 --- a/drivers/gpu/nvgpu/gp106/acr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c | |||
@@ -20,6 +20,7 @@ | |||
20 | #include <nvgpu/dma.h> | 20 | #include <nvgpu/dma.h> |
21 | #include <nvgpu/acr/nvgpu_acr.h> | 21 | #include <nvgpu/acr/nvgpu_acr.h> |
22 | #include <nvgpu/firmware.h> | 22 | #include <nvgpu/firmware.h> |
23 | #include <nvgpu/pmu.h> | ||
23 | 24 | ||
24 | #include "gk20a/gk20a.h" | 25 | #include "gk20a/gk20a.h" |
25 | #include "gk20a/pmu_gk20a.h" | 26 | #include "gk20a/pmu_gk20a.h" |
@@ -140,7 +141,7 @@ void gp106_init_secure_pmu(struct gpu_ops *gops) | |||
140 | static int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img) | 141 | static int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img) |
141 | { | 142 | { |
142 | struct nvgpu_firmware *pmu_fw, *pmu_desc, *pmu_sig; | 143 | struct nvgpu_firmware *pmu_fw, *pmu_desc, *pmu_sig; |
143 | struct pmu_gk20a *pmu = &g->pmu; | 144 | struct nvgpu_pmu *pmu = &g->pmu; |
144 | struct lsf_ucode_desc_v1 *lsf_desc; | 145 | struct lsf_ucode_desc_v1 *lsf_desc; |
145 | int err; | 146 | int err; |
146 | 147 | ||
@@ -382,7 +383,7 @@ static int gp106_prepare_ucode_blob(struct gk20a *g) | |||
382 | 383 | ||
383 | int err; | 384 | int err; |
384 | struct ls_flcn_mgr_v1 lsfm_l, *plsfm; | 385 | struct ls_flcn_mgr_v1 lsfm_l, *plsfm; |
385 | struct pmu_gk20a *pmu = &g->pmu; | 386 | struct nvgpu_pmu *pmu = &g->pmu; |
386 | struct wpr_carveout_info wpr_inf; | 387 | struct wpr_carveout_info wpr_inf; |
387 | 388 | ||
388 | if (g->acr.ucode_blob.cpu_va) { | 389 | if (g->acr.ucode_blob.cpu_va) { |
@@ -445,7 +446,7 @@ static u8 lsfm_falcon_disabled(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm, | |||
445 | static int lsfm_discover_ucode_images(struct gk20a *g, | 446 | static int lsfm_discover_ucode_images(struct gk20a *g, |
446 | struct ls_flcn_mgr_v1 *plsfm) | 447 | struct ls_flcn_mgr_v1 *plsfm) |
447 | { | 448 | { |
448 | struct pmu_gk20a *pmu = &g->pmu; | 449 | struct nvgpu_pmu *pmu = &g->pmu; |
449 | struct flcn_ucode_img_v1 ucode_img; | 450 | struct flcn_ucode_img_v1 ucode_img; |
450 | u32 falcon_id; | 451 | u32 falcon_id; |
451 | u32 i; | 452 | u32 i; |
@@ -531,7 +532,7 @@ static int gp106_pmu_populate_loader_cfg(struct gk20a *g, | |||
531 | void *lsfm, u32 *p_bl_gen_desc_size) | 532 | void *lsfm, u32 *p_bl_gen_desc_size) |
532 | { | 533 | { |
533 | struct wpr_carveout_info wpr_inf; | 534 | struct wpr_carveout_info wpr_inf; |
534 | struct pmu_gk20a *pmu = &g->pmu; | 535 | struct nvgpu_pmu *pmu = &g->pmu; |
535 | struct lsfm_managed_ucode_img_v2 *p_lsfm = | 536 | struct lsfm_managed_ucode_img_v2 *p_lsfm = |
536 | (struct lsfm_managed_ucode_img_v2 *)lsfm; | 537 | (struct lsfm_managed_ucode_img_v2 *)lsfm; |
537 | struct flcn_ucode_img_v1 *p_img = &(p_lsfm->ucode_img); | 538 | struct flcn_ucode_img_v1 *p_img = &(p_lsfm->ucode_img); |
@@ -661,7 +662,7 @@ static int lsfm_fill_flcn_bl_gen_desc(struct gk20a *g, | |||
661 | struct lsfm_managed_ucode_img_v2 *pnode) | 662 | struct lsfm_managed_ucode_img_v2 *pnode) |
662 | { | 663 | { |
663 | 664 | ||
664 | struct pmu_gk20a *pmu = &g->pmu; | 665 | struct nvgpu_pmu *pmu = &g->pmu; |
665 | if (pnode->wpr_header.falcon_id != pmu->falcon_id) { | 666 | if (pnode->wpr_header.falcon_id != pmu->falcon_id) { |
666 | gp106_dbg_pmu("non pmu. write flcn bl gen desc\n"); | 667 | gp106_dbg_pmu("non pmu. write flcn bl gen desc\n"); |
667 | g->ops.pmu.flcn_populate_bl_dmem_desc(g, | 668 | g->ops.pmu.flcn_populate_bl_dmem_desc(g, |
@@ -818,7 +819,7 @@ static void lsfm_fill_static_lsb_hdr_info(struct gk20a *g, | |||
818 | u32 falcon_id, struct lsfm_managed_ucode_img_v2 *pnode) | 819 | u32 falcon_id, struct lsfm_managed_ucode_img_v2 *pnode) |
819 | { | 820 | { |
820 | 821 | ||
821 | struct pmu_gk20a *pmu = &g->pmu; | 822 | struct nvgpu_pmu *pmu = &g->pmu; |
822 | u32 full_app_size = 0; | 823 | u32 full_app_size = 0; |
823 | u32 data = 0; | 824 | u32 data = 0; |
824 | 825 | ||
diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_gp106.c index 467c50be..89144c2a 100644 --- a/drivers/gpu/nvgpu/gp106/pmu_gp106.c +++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.c | |||
@@ -11,6 +11,8 @@ | |||
11 | * more details. | 11 | * more details. |
12 | */ | 12 | */ |
13 | 13 | ||
14 | #include <nvgpu/pmu.h> | ||
15 | |||
14 | #include "gk20a/gk20a.h" | 16 | #include "gk20a/gk20a.h" |
15 | #include "gk20a/pmu_gk20a.h" | 17 | #include "gk20a/pmu_gk20a.h" |
16 | 18 | ||
@@ -31,7 +33,7 @@ | |||
31 | #define PMU_MEM_SCRUBBING_TIMEOUT_MAX 1000 | 33 | #define PMU_MEM_SCRUBBING_TIMEOUT_MAX 1000 |
32 | #define PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT 10 | 34 | #define PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT 10 |
33 | 35 | ||
34 | static int gp106_pmu_enable_hw(struct pmu_gk20a *pmu, bool enable) | 36 | static int gp106_pmu_enable_hw(struct nvgpu_pmu *pmu, bool enable) |
35 | { | 37 | { |
36 | struct gk20a *g = gk20a_from_pmu(pmu); | 38 | struct gk20a *g = gk20a_from_pmu(pmu); |
37 | 39 | ||
@@ -86,7 +88,7 @@ static int gp106_pmu_enable_hw(struct pmu_gk20a *pmu, bool enable) | |||
86 | } | 88 | } |
87 | } | 89 | } |
88 | 90 | ||
89 | static int pmu_enable(struct pmu_gk20a *pmu, bool enable) | 91 | static int pmu_enable(struct nvgpu_pmu *pmu, bool enable) |
90 | { | 92 | { |
91 | struct gk20a *g = gk20a_from_pmu(pmu); | 93 | struct gk20a *g = gk20a_from_pmu(pmu); |
92 | u32 reg_reset; | 94 | u32 reg_reset; |
@@ -121,7 +123,7 @@ static int pmu_enable(struct pmu_gk20a *pmu, bool enable) | |||
121 | 123 | ||
122 | int gp106_pmu_reset(struct gk20a *g) | 124 | int gp106_pmu_reset(struct gk20a *g) |
123 | { | 125 | { |
124 | struct pmu_gk20a *pmu = &g->pmu; | 126 | struct nvgpu_pmu *pmu = &g->pmu; |
125 | int err = 0; | 127 | int err = 0; |
126 | 128 | ||
127 | gk20a_dbg_fn(""); | 129 | gk20a_dbg_fn(""); |
@@ -210,7 +212,7 @@ static void pmu_handle_param_msg(struct gk20a *g, struct pmu_msg *msg, | |||
210 | 212 | ||
211 | static int gp106_pg_param_init(struct gk20a *g, u32 pg_engine_id) | 213 | static int gp106_pg_param_init(struct gk20a *g, u32 pg_engine_id) |
212 | { | 214 | { |
213 | struct pmu_gk20a *pmu = &g->pmu; | 215 | struct nvgpu_pmu *pmu = &g->pmu; |
214 | struct pmu_cmd cmd; | 216 | struct pmu_cmd cmd; |
215 | u32 seq; | 217 | u32 seq; |
216 | u32 status; | 218 | u32 status; |
@@ -262,7 +264,7 @@ static int gp106_pg_param_init(struct gk20a *g, u32 pg_engine_id) | |||
262 | void gp106_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, | 264 | void gp106_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, |
263 | struct pmu_pg_stats_data *pg_stat_data) | 265 | struct pmu_pg_stats_data *pg_stat_data) |
264 | { | 266 | { |
265 | struct pmu_gk20a *pmu = &g->pmu; | 267 | struct nvgpu_pmu *pmu = &g->pmu; |
266 | struct pmu_pg_stats_v2 stats; | 268 | struct pmu_pg_stats_v2 stats; |
267 | 269 | ||
268 | pmu_copy_from_dmem(pmu, | 270 | pmu_copy_from_dmem(pmu, |
@@ -335,7 +337,7 @@ static bool gp106_is_priv_load(u32 falcon_id) | |||
335 | static void gp106_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask, | 337 | static void gp106_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask, |
336 | u32 flags) | 338 | u32 flags) |
337 | { | 339 | { |
338 | struct pmu_gk20a *pmu = &g->pmu; | 340 | struct nvgpu_pmu *pmu = &g->pmu; |
339 | struct pmu_cmd cmd; | 341 | struct pmu_cmd cmd; |
340 | u32 seq; | 342 | u32 seq; |
341 | 343 | ||
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c index 078a1436..9c86c5b5 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c | |||
@@ -11,6 +11,8 @@ | |||
11 | * more details. | 11 | * more details. |
12 | */ | 12 | */ |
13 | 13 | ||
14 | #include <nvgpu/pmu.h> | ||
15 | |||
14 | #include "gk20a/gk20a.h" | 16 | #include "gk20a/gk20a.h" |
15 | #include "gk20a/pmu_gk20a.h" | 17 | #include "gk20a/pmu_gk20a.h" |
16 | 18 | ||
@@ -88,7 +90,7 @@ int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout) | |||
88 | return completion; | 90 | return completion; |
89 | } | 91 | } |
90 | 92 | ||
91 | void sec2_copy_to_dmem(struct pmu_gk20a *pmu, | 93 | void sec2_copy_to_dmem(struct nvgpu_pmu *pmu, |
92 | u32 dst, u8 *src, u32 size, u8 port) | 94 | u32 dst, u8 *src, u32 size, u8 port) |
93 | { | 95 | { |
94 | struct gk20a *g = gk20a_from_pmu(pmu); | 96 | struct gk20a *g = gk20a_from_pmu(pmu); |
@@ -139,7 +141,7 @@ void sec2_copy_to_dmem(struct pmu_gk20a *pmu, | |||
139 | return; | 141 | return; |
140 | } | 142 | } |
141 | 143 | ||
142 | int bl_bootstrap_sec2(struct pmu_gk20a *pmu, | 144 | int bl_bootstrap_sec2(struct nvgpu_pmu *pmu, |
143 | void *desc, u32 bl_sz) | 145 | void *desc, u32 bl_sz) |
144 | { | 146 | { |
145 | struct gk20a *g = gk20a_from_pmu(pmu); | 147 | struct gk20a *g = gk20a_from_pmu(pmu); |
@@ -223,7 +225,7 @@ int bl_bootstrap_sec2(struct pmu_gk20a *pmu, | |||
223 | return 0; | 225 | return 0; |
224 | } | 226 | } |
225 | 227 | ||
226 | void sec_enable_irq(struct pmu_gk20a *pmu, bool enable) | 228 | void sec_enable_irq(struct nvgpu_pmu *pmu, bool enable) |
227 | { | 229 | { |
228 | struct gk20a *g = gk20a_from_pmu(pmu); | 230 | struct gk20a *g = gk20a_from_pmu(pmu); |
229 | 231 | ||
@@ -281,7 +283,7 @@ void sec_enable_irq(struct pmu_gk20a *pmu, bool enable) | |||
281 | void init_pmu_setup_hw1(struct gk20a *g) | 283 | void init_pmu_setup_hw1(struct gk20a *g) |
282 | { | 284 | { |
283 | struct mm_gk20a *mm = &g->mm; | 285 | struct mm_gk20a *mm = &g->mm; |
284 | struct pmu_gk20a *pmu = &g->pmu; | 286 | struct nvgpu_pmu *pmu = &g->pmu; |
285 | 287 | ||
286 | /* PMU TRANSCFG */ | 288 | /* PMU TRANSCFG */ |
287 | /* setup apertures - virtual */ | 289 | /* setup apertures - virtual */ |
@@ -331,7 +333,7 @@ void init_pmu_setup_hw1(struct gk20a *g) | |||
331 | int init_sec2_setup_hw1(struct gk20a *g, | 333 | int init_sec2_setup_hw1(struct gk20a *g, |
332 | void *desc, u32 bl_sz) | 334 | void *desc, u32 bl_sz) |
333 | { | 335 | { |
334 | struct pmu_gk20a *pmu = &g->pmu; | 336 | struct nvgpu_pmu *pmu = &g->pmu; |
335 | int err; | 337 | int err; |
336 | u32 data = 0; | 338 | u32 data = 0; |
337 | 339 | ||
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.h b/drivers/gpu/nvgpu/gp106/sec2_gp106.h index 336bb0f0..e3da0abf 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.h +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -16,12 +16,12 @@ | |||
16 | 16 | ||
17 | int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout); | 17 | int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout); |
18 | int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout); | 18 | int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout); |
19 | void sec2_copy_to_dmem(struct pmu_gk20a *pmu, | 19 | void sec2_copy_to_dmem(struct nvgpu_pmu *pmu, |
20 | u32 dst, u8 *src, u32 size, u8 port); | 20 | u32 dst, u8 *src, u32 size, u8 port); |
21 | void sec2_dump_falcon_stats(struct pmu_gk20a *pmu); | 21 | void sec2_dump_falcon_stats(struct nvgpu_pmu *pmu); |
22 | int bl_bootstrap_sec2(struct pmu_gk20a *pmu, | 22 | int bl_bootstrap_sec2(struct nvgpu_pmu *pmu, |
23 | void *desc, u32 bl_sz); | 23 | void *desc, u32 bl_sz); |
24 | void sec_enable_irq(struct pmu_gk20a *pmu, bool enable); | 24 | void sec_enable_irq(struct nvgpu_pmu *pmu, bool enable); |
25 | void init_pmu_setup_hw1(struct gk20a *g); | 25 | void init_pmu_setup_hw1(struct gk20a *g); |
26 | int init_sec2_setup_hw1(struct gk20a *g, | 26 | int init_sec2_setup_hw1(struct gk20a *g, |
27 | void *desc, u32 bl_sz); | 27 | void *desc, u32 bl_sz); |