diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp106')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/fifo_gp106.c | 11 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/fifo_gp106.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 68 |
3 files changed, 71 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/gp106/fifo_gp106.c b/drivers/gpu/nvgpu/gp106/fifo_gp106.c index 5fa03d6f..22a49260 100644 --- a/drivers/gpu/nvgpu/gp106/fifo_gp106.c +++ b/drivers/gpu/nvgpu/gp106/fifo_gp106.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -19,14 +19,7 @@ | |||
19 | #include <nvgpu/hw/gp106/hw_ccsr_gp106.h> | 19 | #include <nvgpu/hw/gp106/hw_ccsr_gp106.h> |
20 | #include <nvgpu/hw/gp106/hw_fifo_gp106.h> | 20 | #include <nvgpu/hw/gp106/hw_fifo_gp106.h> |
21 | 21 | ||
22 | static u32 gp106_fifo_get_num_fifos(struct gk20a *g) | 22 | u32 gp106_fifo_get_num_fifos(struct gk20a *g) |
23 | { | 23 | { |
24 | return ccsr_channel__size_1_v(); | 24 | return ccsr_channel__size_1_v(); |
25 | } | 25 | } |
26 | |||
27 | void gp106_init_fifo(struct gpu_ops *gops) | ||
28 | { | ||
29 | gp10b_init_fifo(gops); | ||
30 | gops->fifo.get_num_fifos = gp106_fifo_get_num_fifos; | ||
31 | gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; | ||
32 | } | ||
diff --git a/drivers/gpu/nvgpu/gp106/fifo_gp106.h b/drivers/gpu/nvgpu/gp106/fifo_gp106.h index 1bcec9ef..c70c0995 100644 --- a/drivers/gpu/nvgpu/gp106/fifo_gp106.h +++ b/drivers/gpu/nvgpu/gp106/fifo_gp106.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -13,6 +13,6 @@ | |||
13 | 13 | ||
14 | #ifndef NVGPU_FIFO_GP106_H | 14 | #ifndef NVGPU_FIFO_GP106_H |
15 | #define NVGPU_FIFO_GP106_H | 15 | #define NVGPU_FIFO_GP106_H |
16 | struct gpu_ops; | 16 | struct gk20a; |
17 | void gp106_init_fifo(struct gpu_ops *gops); | 17 | u32 gp106_fifo_get_num_fifos(struct gk20a *g); |
18 | #endif | 18 | #endif |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 1690c42b..fa767c3b 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -14,6 +14,7 @@ | |||
14 | */ | 14 | */ |
15 | 15 | ||
16 | #include "gk20a/gk20a.h" | 16 | #include "gk20a/gk20a.h" |
17 | #include "gk20a/fifo_gk20a.h" | ||
17 | #include "gk20a/dbg_gpu_gk20a.h" | 18 | #include "gk20a/dbg_gpu_gk20a.h" |
18 | #include "gk20a/css_gr_gk20a.h" | 19 | #include "gk20a/css_gr_gk20a.h" |
19 | #include "gk20a/bus_gk20a.h" | 20 | #include "gk20a/bus_gk20a.h" |
@@ -31,6 +32,7 @@ | |||
31 | #include "gp10b/regops_gp10b.h" | 32 | #include "gp10b/regops_gp10b.h" |
32 | #include "gp10b/cde_gp10b.h" | 33 | #include "gp10b/cde_gp10b.h" |
33 | #include "gp10b/priv_ring_gp10b.h" | 34 | #include "gp10b/priv_ring_gp10b.h" |
35 | #include "gp10b/fifo_gp10b.h" | ||
34 | 36 | ||
35 | #include "gp106/fifo_gp106.h" | 37 | #include "gp106/fifo_gp106.h" |
36 | #include "gp106/regops_gp106.h" | 38 | #include "gp106/regops_gp106.h" |
@@ -62,6 +64,9 @@ | |||
62 | #include <nvgpu/bus.h> | 64 | #include <nvgpu/bus.h> |
63 | 65 | ||
64 | #include <nvgpu/hw/gp106/hw_proj_gp106.h> | 66 | #include <nvgpu/hw/gp106/hw_proj_gp106.h> |
67 | #include <nvgpu/hw/gp106/hw_fifo_gp106.h> | ||
68 | #include <nvgpu/hw/gp106/hw_ram_gp106.h> | ||
69 | #include <nvgpu/hw/gp106/hw_top_gp106.h> | ||
65 | 70 | ||
66 | static int gp106_get_litter_value(struct gk20a *g, int value) | 71 | static int gp106_get_litter_value(struct gk20a *g, int value) |
67 | { | 72 | { |
@@ -243,6 +248,66 @@ static const struct gpu_ops gp106_ops = { | |||
243 | .pg_gr_load_gating_prod = | 248 | .pg_gr_load_gating_prod = |
244 | gr_gp106_pg_gr_load_gating_prod, | 249 | gr_gp106_pg_gr_load_gating_prod, |
245 | }, | 250 | }, |
251 | .fifo = { | ||
252 | .init_fifo_setup_hw = gk20a_init_fifo_setup_hw, | ||
253 | .bind_channel = channel_gm20b_bind, | ||
254 | .unbind_channel = gk20a_fifo_channel_unbind, | ||
255 | .disable_channel = gk20a_fifo_disable_channel, | ||
256 | .enable_channel = gk20a_fifo_enable_channel, | ||
257 | .alloc_inst = gk20a_fifo_alloc_inst, | ||
258 | .free_inst = gk20a_fifo_free_inst, | ||
259 | .setup_ramfc = channel_gp10b_setup_ramfc, | ||
260 | .channel_set_priority = gk20a_fifo_set_priority, | ||
261 | .channel_set_timeslice = gk20a_fifo_set_timeslice, | ||
262 | .default_timeslice_us = gk20a_fifo_default_timeslice_us, | ||
263 | .setup_userd = gk20a_fifo_setup_userd, | ||
264 | .userd_gp_get = gk20a_fifo_userd_gp_get, | ||
265 | .userd_gp_put = gk20a_fifo_userd_gp_put, | ||
266 | .userd_pb_get = gk20a_fifo_userd_pb_get, | ||
267 | .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, | ||
268 | .preempt_channel = gk20a_fifo_preempt_channel, | ||
269 | .preempt_tsg = gk20a_fifo_preempt_tsg, | ||
270 | .update_runlist = gk20a_fifo_update_runlist, | ||
271 | .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault, | ||
272 | .get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info, | ||
273 | .wait_engine_idle = gk20a_fifo_wait_engine_idle, | ||
274 | .get_num_fifos = gp106_fifo_get_num_fifos, | ||
275 | .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, | ||
276 | .set_runlist_interleave = gk20a_fifo_set_runlist_interleave, | ||
277 | .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice, | ||
278 | .force_reset_ch = gk20a_fifo_force_reset_ch, | ||
279 | .engine_enum_from_type = gp10b_fifo_engine_enum_from_type, | ||
280 | .device_info_data_parse = gp10b_device_info_data_parse, | ||
281 | .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v, | ||
282 | .init_engine_info = gk20a_fifo_init_engine_info, | ||
283 | .runlist_entry_size = ram_rl_entry_size_v, | ||
284 | .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry, | ||
285 | .get_ch_runlist_entry = gk20a_get_ch_runlist_entry, | ||
286 | .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc, | ||
287 | .dump_pbdma_status = gk20a_dump_pbdma_status, | ||
288 | .dump_eng_status = gk20a_dump_eng_status, | ||
289 | .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc, | ||
290 | .intr_0_error_mask = gk20a_fifo_intr_0_error_mask, | ||
291 | .is_preempt_pending = gk20a_fifo_is_preempt_pending, | ||
292 | .init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs, | ||
293 | .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, | ||
294 | .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg, | ||
295 | .handle_sched_error = gk20a_fifo_handle_sched_error, | ||
296 | .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0, | ||
297 | .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1, | ||
298 | .tsg_bind_channel = gk20a_tsg_bind_channel, | ||
299 | .tsg_unbind_channel = gk20a_tsg_unbind_channel, | ||
300 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | ||
301 | .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf, | ||
302 | .free_syncpt_buf = gk20a_fifo_free_syncpt_buf, | ||
303 | .add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd, | ||
304 | .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size, | ||
305 | .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd, | ||
306 | .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size, | ||
307 | #endif | ||
308 | .resetup_ramfc = gp10b_fifo_resetup_ramfc, | ||
309 | .device_info_fault_id = top_device_info_data_fault_id_enum_v, | ||
310 | }, | ||
246 | .mc = { | 311 | .mc = { |
247 | .intr_enable = mc_gp10b_intr_enable, | 312 | .intr_enable = mc_gp10b_intr_enable, |
248 | .intr_unit_config = mc_gp10b_intr_unit_config, | 313 | .intr_unit_config = mc_gp10b_intr_unit_config, |
@@ -331,6 +396,7 @@ int gp106_init_hal(struct gk20a *g) | |||
331 | 396 | ||
332 | gops->ltc = gp106_ops.ltc; | 397 | gops->ltc = gp106_ops.ltc; |
333 | gops->clock_gating = gp106_ops.clock_gating; | 398 | gops->clock_gating = gp106_ops.clock_gating; |
399 | gops->fifo = gp106_ops.fifo; | ||
334 | gops->mc = gp106_ops.mc; | 400 | gops->mc = gp106_ops.mc; |
335 | gops->debug = gp106_ops.debug; | 401 | gops->debug = gp106_ops.debug; |
336 | gops->dbg_session_ops = gp106_ops.dbg_session_ops; | 402 | gops->dbg_session_ops = gp106_ops.dbg_session_ops; |
@@ -358,7 +424,6 @@ int gp106_init_hal(struct gk20a *g) | |||
358 | gp106_init_gr(gops); | 424 | gp106_init_gr(gops); |
359 | gp10b_init_fecs_trace_ops(gops); | 425 | gp10b_init_fecs_trace_ops(gops); |
360 | gp106_init_fb(gops); | 426 | gp106_init_fb(gops); |
361 | gp106_init_fifo(gops); | ||
362 | gp10b_init_ce(gops); | 427 | gp10b_init_ce(gops); |
363 | gp106_init_gr_ctx(gops); | 428 | gp106_init_gr_ctx(gops); |
364 | gp106_init_mm(gops); | 429 | gp106_init_mm(gops); |
@@ -366,7 +431,6 @@ int gp106_init_hal(struct gk20a *g) | |||
366 | gp106_init_clk_ops(gops); | 431 | gp106_init_clk_ops(gops); |
367 | gp106_init_clk_arb_ops(gops); | 432 | gp106_init_clk_arb_ops(gops); |
368 | gp106_init_regops(gops); | 433 | gp106_init_regops(gops); |
369 | gk20a_init_tsg_ops(gops); | ||
370 | gk20a_init_pramin_ops(gops); | 434 | gk20a_init_pramin_ops(gops); |
371 | gp106_init_therm_ops(gops); | 435 | gp106_init_therm_ops(gops); |
372 | 436 | ||