diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp106')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/sec2_gp106.c | 5 |
2 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 1246ee7f..59f72e13 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -524,6 +524,7 @@ static const struct gpu_ops gp106_ops = { | |||
524 | .init_pdb = gp10b_mm_init_pdb, | 524 | .init_pdb = gp10b_mm_init_pdb, |
525 | .init_mm_setup_hw = gp10b_init_mm_setup_hw, | 525 | .init_mm_setup_hw = gp10b_init_mm_setup_hw, |
526 | .is_bar1_supported = gm20b_mm_is_bar1_supported, | 526 | .is_bar1_supported = gm20b_mm_is_bar1_supported, |
527 | .alloc_inst_block = gk20a_alloc_inst_block, | ||
527 | .init_inst_block = gk20a_init_inst_block, | 528 | .init_inst_block = gk20a_init_inst_block, |
528 | .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, | 529 | .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, |
529 | .init_bar2_vm = gb10b_init_bar2_vm, | 530 | .init_bar2_vm = gb10b_init_bar2_vm, |
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c index 9f0fe375..26ded39e 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c | |||
@@ -22,6 +22,7 @@ | |||
22 | 22 | ||
23 | #include <nvgpu/pmu.h> | 23 | #include <nvgpu/pmu.h> |
24 | #include <nvgpu/falcon.h> | 24 | #include <nvgpu/falcon.h> |
25 | #include <nvgpu/mm.h> | ||
25 | 26 | ||
26 | #include "gk20a/gk20a.h" | 27 | #include "gk20a/gk20a.h" |
27 | #include "sec2_gp106.h" | 28 | #include "sec2_gp106.h" |
@@ -88,7 +89,7 @@ int bl_bootstrap_sec2(struct nvgpu_pmu *pmu, | |||
88 | 89 | ||
89 | gk20a_writel(g, psec_falcon_nxtctx_r(), | 90 | gk20a_writel(g, psec_falcon_nxtctx_r(), |
90 | pwr_pmu_new_instblk_ptr_f( | 91 | pwr_pmu_new_instblk_ptr_f( |
91 | gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | | 92 | nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | |
92 | pwr_pmu_new_instblk_valid_f(1) | | 93 | pwr_pmu_new_instblk_valid_f(1) | |
93 | nvgpu_aperture_mask(g, &mm->pmu.inst_block, | 94 | nvgpu_aperture_mask(g, &mm->pmu.inst_block, |
94 | pwr_pmu_new_instblk_target_sys_coh_f(), | 95 | pwr_pmu_new_instblk_target_sys_coh_f(), |
@@ -154,7 +155,7 @@ void init_pmu_setup_hw1(struct gk20a *g) | |||
154 | pwr_falcon_itfen_ctxen_enable_f()); | 155 | pwr_falcon_itfen_ctxen_enable_f()); |
155 | gk20a_writel(g, pwr_pmu_new_instblk_r(), | 156 | gk20a_writel(g, pwr_pmu_new_instblk_r(), |
156 | pwr_pmu_new_instblk_ptr_f( | 157 | pwr_pmu_new_instblk_ptr_f( |
157 | gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | | 158 | nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | |
158 | pwr_pmu_new_instblk_valid_f(1) | | 159 | pwr_pmu_new_instblk_valid_f(1) | |
159 | nvgpu_aperture_mask(g, &mm->pmu.inst_block, | 160 | nvgpu_aperture_mask(g, &mm->pmu.inst_block, |
160 | pwr_pmu_new_instblk_target_sys_coh_f(), | 161 | pwr_pmu_new_instblk_target_sys_coh_f(), |