2 files changed, 2 insertions, 8 deletions

diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_gp106.c
index cadbd308..308bcf04 100644
--- a/drivers/gpu/nvgpu/gp106/pmu_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.c
@@ -71,7 +71,7 @@ static int gp106_pmu_enable_hw(struct pmu_gk20a *pmu, bool enable)
                                 return 0;
                         }
                         udelay(PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT);
-                } while (--retries || !tegra_platform_is_silicon());
+                } while (--retries);
 
                 /* If scrubbing timeout, keep PMU in reset state */
                 gk20a_writel(g, pwr_falcon_engine_r(),
diff --git a/drivers/gpu/nvgpu/gp106/therm_gp106.c b/drivers/gpu/nvgpu/gp106/therm_gp106.c
index bf8fbfe7..761d1b89 100644
--- a/drivers/gpu/nvgpu/gp106/therm_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/therm_gp106.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -87,12 +87,6 @@ static int gp106_elcg_init_idle_filters(struct gk20a *g)
                 active_engine_id = f->active_engines_list[engine_id];
                 gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
 
-                if (tegra_platform_is_linsim()) {
-                        gate_ctrl = set_field(gate_ctrl,
-                                therm_gate_ctrl_eng_delay_after_m(),
-                                therm_gate_ctrl_eng_delay_after_f(4));
-                }
-
                 gate_ctrl = set_field(gate_ctrl,
                         therm_gate_ctrl_eng_idle_filt_exp_m(),
                         therm_gate_ctrl_eng_idle_filt_exp_f(2));