diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp106')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/clk_gp106.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/mclk_gp106.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/pmu_gp106.c | 4 |
3 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.c b/drivers/gpu/nvgpu/gp106/clk_gp106.c index 13a401f0..e892ceda 100644 --- a/drivers/gpu/nvgpu/gp106/clk_gp106.c +++ b/drivers/gpu/nvgpu/gp106/clk_gp106.c | |||
@@ -188,7 +188,7 @@ u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) | |||
188 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f()); | 188 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f()); |
189 | 189 | ||
190 | /* Force wb() */ | 190 | /* Force wb() */ |
191 | gk20a_readl(g, c->cntr.reg_ctrl_addr); | 191 | (void) gk20a_readl(g, c->cntr.reg_ctrl_addr); |
192 | 192 | ||
193 | /* Wait for reset to happen */ | 193 | /* Wait for reset to happen */ |
194 | retries = CLK_DEFAULT_CNTRL_SETTLE_RETRIES; | 194 | retries = CLK_DEFAULT_CNTRL_SETTLE_RETRIES; |
@@ -209,7 +209,7 @@ u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) | |||
209 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() | | 209 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() | |
210 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_f(XTAL_CNTR_CLKS) | | 210 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_f(XTAL_CNTR_CLKS) | |
211 | c->cntr.reg_ctrl_idx); | 211 | c->cntr.reg_ctrl_idx); |
212 | gk20a_readl(g, c->cntr.reg_ctrl_addr); | 212 | (void) gk20a_readl(g, c->cntr.reg_ctrl_addr); |
213 | 213 | ||
214 | nvgpu_udelay(XTAL_CNTR_DELAY); | 214 | nvgpu_udelay(XTAL_CNTR_DELAY); |
215 | 215 | ||
@@ -220,9 +220,9 @@ read_err: | |||
220 | gk20a_writel(g, c->cntr.reg_ctrl_addr, | 220 | gk20a_writel(g, c->cntr.reg_ctrl_addr, |
221 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_asserted_f() | | 221 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_asserted_f() | |
222 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f()); | 222 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f()); |
223 | gk20a_readl(g, c->cntr.reg_ctrl_addr); | 223 | (void) gk20a_readl(g, c->cntr.reg_ctrl_addr); |
224 | gk20a_writel(g, c->cntr.reg_ctrl_addr, save_reg); | 224 | gk20a_writel(g, c->cntr.reg_ctrl_addr, save_reg); |
225 | gk20a_readl(g, c->cntr.reg_ctrl_addr); | 225 | (void) gk20a_readl(g, c->cntr.reg_ctrl_addr); |
226 | nvgpu_mutex_release(&clk->clk_mutex); | 226 | nvgpu_mutex_release(&clk->clk_mutex); |
227 | 227 | ||
228 | return cntr; | 228 | return cntr; |
diff --git a/drivers/gpu/nvgpu/gp106/mclk_gp106.c b/drivers/gpu/nvgpu/gp106/mclk_gp106.c index 36092a1a..6a49e83b 100644 --- a/drivers/gpu/nvgpu/gp106/mclk_gp106.c +++ b/drivers/gpu/nvgpu/gp106/mclk_gp106.c | |||
@@ -3371,8 +3371,8 @@ int gp106_mclk_change(struct gk20a *g, u16 val) | |||
3371 | if (speed == GP106_MCLK_HIGH_SPEED) { | 3371 | if (speed == GP106_MCLK_HIGH_SPEED) { |
3372 | gk20a_writel(g, 0x132000, 0x98010000); | 3372 | gk20a_writel(g, 0x132000, 0x98010000); |
3373 | /* Introduce delay */ | 3373 | /* Introduce delay */ |
3374 | gk20a_readl(g, 0x132000); | 3374 | (void) gk20a_readl(g, 0x132000); |
3375 | gk20a_readl(g, 0x132000); | 3375 | (void) gk20a_readl(g, 0x132000); |
3376 | } | 3376 | } |
3377 | 3377 | ||
3378 | gk20a_writel(g, 0x137300, 0x20000103); | 3378 | gk20a_writel(g, 0x137300, 0x20000103); |
diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_gp106.c index 963668c4..031ac7d8 100644 --- a/drivers/gpu/nvgpu/gp106/pmu_gp106.c +++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.c | |||
@@ -71,11 +71,11 @@ int gp106_pmu_engine_reset(struct gk20a *g, bool do_reset) | |||
71 | if (do_reset) { | 71 | if (do_reset) { |
72 | gk20a_writel(g, pwr_falcon_engine_r(), | 72 | gk20a_writel(g, pwr_falcon_engine_r(), |
73 | pwr_falcon_engine_reset_false_f()); | 73 | pwr_falcon_engine_reset_false_f()); |
74 | gk20a_readl(g, pwr_falcon_engine_r()); | 74 | (void) gk20a_readl(g, pwr_falcon_engine_r()); |
75 | } else { | 75 | } else { |
76 | gk20a_writel(g, pwr_falcon_engine_r(), | 76 | gk20a_writel(g, pwr_falcon_engine_r(), |
77 | pwr_falcon_engine_reset_true_f()); | 77 | pwr_falcon_engine_reset_true_f()); |
78 | gk20a_readl(g, pwr_falcon_engine_r()); | 78 | (void) gk20a_readl(g, pwr_falcon_engine_r()); |
79 | } | 79 | } |
80 | 80 | ||
81 | return 0; | 81 | return 0; |