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Diffstat (limited to 'drivers/gpu/nvgpu/gp106/sec2_gp106.h')
-rw-r--r--drivers/gpu/nvgpu/gp106/sec2_gp106.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.h b/drivers/gpu/nvgpu/gp106/sec2_gp106.h
index 336bb0f0..e3da0abf 100644
--- a/drivers/gpu/nvgpu/gp106/sec2_gp106.h
+++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -16,12 +16,12 @@
16 16
17int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout); 17int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout);
18int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout); 18int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout);
19void sec2_copy_to_dmem(struct pmu_gk20a *pmu, 19void sec2_copy_to_dmem(struct nvgpu_pmu *pmu,
20 u32 dst, u8 *src, u32 size, u8 port); 20 u32 dst, u8 *src, u32 size, u8 port);
21void sec2_dump_falcon_stats(struct pmu_gk20a *pmu); 21void sec2_dump_falcon_stats(struct nvgpu_pmu *pmu);
22int bl_bootstrap_sec2(struct pmu_gk20a *pmu, 22int bl_bootstrap_sec2(struct nvgpu_pmu *pmu,
23 void *desc, u32 bl_sz); 23 void *desc, u32 bl_sz);
24void sec_enable_irq(struct pmu_gk20a *pmu, bool enable); 24void sec_enable_irq(struct nvgpu_pmu *pmu, bool enable);
25void init_pmu_setup_hw1(struct gk20a *g); 25void init_pmu_setup_hw1(struct gk20a *g);
26int init_sec2_setup_hw1(struct gk20a *g, 26int init_sec2_setup_hw1(struct gk20a *g,
27 void *desc, u32 bl_sz); 27 void *desc, u32 bl_sz);