diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/sec2_gp106.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/sec2_gp106.c | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c index 0032bce7..dd67f882 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c | |||
@@ -35,10 +35,10 @@ | |||
35 | int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout) | 35 | int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout) |
36 | { | 36 | { |
37 | u32 data = 0; | 37 | u32 data = 0; |
38 | unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout); | 38 | struct nvgpu_timeout to; |
39 | 39 | ||
40 | while (time_before(jiffies, end_jiffies) || | 40 | nvgpu_timeout_init(g, &to, timeout, NVGPU_TIMER_CPU_TIMER); |
41 | !tegra_platform_is_silicon()) { | 41 | do { |
42 | gk20a_writel(g, psec_falcon_irqsclr_r(), | 42 | gk20a_writel(g, psec_falcon_irqsclr_r(), |
43 | gk20a_readl(g, psec_falcon_irqsclr_r()) | (0x10)); | 43 | gk20a_readl(g, psec_falcon_irqsclr_r()) | (0x10)); |
44 | data = gk20a_readl(g, psec_falcon_irqstat_r()); | 44 | data = gk20a_readl(g, psec_falcon_irqstat_r()); |
@@ -46,10 +46,10 @@ int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout) | |||
46 | psec_falcon_irqstat_halt_true_f()) | 46 | psec_falcon_irqstat_halt_true_f()) |
47 | /*halt irq is clear*/ | 47 | /*halt irq is clear*/ |
48 | break; | 48 | break; |
49 | timeout--; | ||
50 | udelay(1); | 49 | udelay(1); |
51 | } | 50 | } while (!nvgpu_timeout_expired(&to)); |
52 | if (timeout == 0) | 51 | |
52 | if (nvgpu_timeout_peek_expired(&to)) | ||
53 | return -EBUSY; | 53 | return -EBUSY; |
54 | return 0; | 54 | return 0; |
55 | } | 55 | } |
@@ -58,10 +58,10 @@ int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout) | |||
58 | { | 58 | { |
59 | u32 data = 0; | 59 | u32 data = 0; |
60 | int completion = -EBUSY; | 60 | int completion = -EBUSY; |
61 | unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout); | 61 | struct nvgpu_timeout to; |
62 | 62 | ||
63 | while (time_before(jiffies, end_jiffies) || | 63 | nvgpu_timeout_init(g, &to, timeout, NVGPU_TIMER_CPU_TIMER); |
64 | !tegra_platform_is_silicon()) { | 64 | do { |
65 | data = gk20a_readl(g, psec_falcon_cpuctl_r()); | 65 | data = gk20a_readl(g, psec_falcon_cpuctl_r()); |
66 | if (data & psec_falcon_cpuctl_halt_intr_m()) { | 66 | if (data & psec_falcon_cpuctl_halt_intr_m()) { |
67 | /*CPU is halted break*/ | 67 | /*CPU is halted break*/ |
@@ -69,21 +69,21 @@ int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout) | |||
69 | break; | 69 | break; |
70 | } | 70 | } |
71 | udelay(1); | 71 | udelay(1); |
72 | } | 72 | } while (!nvgpu_timeout_expired(&to)); |
73 | if (completion){ | 73 | |
74 | if (completion) { | ||
74 | gk20a_err(dev_from_gk20a(g), "ACR boot timed out"); | 75 | gk20a_err(dev_from_gk20a(g), "ACR boot timed out"); |
76 | return completion; | ||
75 | } | 77 | } |
76 | else { | ||
77 | 78 | ||
78 | g->acr.capabilities = gk20a_readl(g, psec_falcon_mailbox1_r()); | 79 | g->acr.capabilities = gk20a_readl(g, psec_falcon_mailbox1_r()); |
79 | gm20b_dbg_pmu("ACR capabilities %x\n", g->acr.capabilities); | 80 | gm20b_dbg_pmu("ACR capabilities %x\n", g->acr.capabilities); |
80 | data = gk20a_readl(g, psec_falcon_mailbox0_r()); | 81 | data = gk20a_readl(g, psec_falcon_mailbox0_r()); |
81 | if (data) { | 82 | if (data) { |
82 | 83 | ||
83 | gk20a_err(dev_from_gk20a(g), | 84 | gk20a_err(dev_from_gk20a(g), |
84 | "ACR boot failed, err %x", data); | 85 | "ACR boot failed, err %x", data); |
85 | completion = -EAGAIN; | 86 | completion = -EAGAIN; |
86 | } | ||
87 | } | 87 | } |
88 | 88 | ||
89 | init_pmu_setup_hw1(g); | 89 | init_pmu_setup_hw1(g); |