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Diffstat (limited to 'drivers/gpu/nvgpu/gp106/sec2_gp106.c')
-rw-r--r--drivers/gpu/nvgpu/gp106/sec2_gp106.c6
1 files changed, 1 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c
index 61424bfe..dec35a91 100644
--- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c
@@ -32,10 +32,6 @@
32#include <nvgpu/hw/gp106/hw_pwr_gp106.h> 32#include <nvgpu/hw/gp106/hw_pwr_gp106.h>
33#include <nvgpu/hw/gp106/hw_psec_gp106.h> 33#include <nvgpu/hw/gp106/hw_psec_gp106.h>
34 34
35/*Defines*/
36#define gm20b_dbg_pmu(g, fmt, arg...) \
37 nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg)
38
39int gp106_sec2_clear_halt_interrupt_status(struct gk20a *g, 35int gp106_sec2_clear_halt_interrupt_status(struct gk20a *g,
40 unsigned int timeout) 36 unsigned int timeout)
41{ 37{
@@ -61,7 +57,7 @@ int gp106_sec2_wait_for_halt(struct gk20a *g, unsigned int timeout)
61 57
62 g->acr.capabilities = nvgpu_flcn_mailbox_read(&g->sec2_flcn, 58 g->acr.capabilities = nvgpu_flcn_mailbox_read(&g->sec2_flcn,
63 FALCON_MAILBOX_1); 59 FALCON_MAILBOX_1);
64 gm20b_dbg_pmu(g, "ACR capabilities %x\n", g->acr.capabilities); 60 nvgpu_pmu_dbg(g, "ACR capabilities %x\n", g->acr.capabilities);
65 data = nvgpu_flcn_mailbox_read(&g->sec2_flcn, FALCON_MAILBOX_0); 61 data = nvgpu_flcn_mailbox_read(&g->sec2_flcn, FALCON_MAILBOX_0);
66 if (data) { 62 if (data) {
67 nvgpu_err(g, "ACR boot failed, err %x", data); 63 nvgpu_err(g, "ACR boot failed, err %x", data);