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path: root/drivers/gpu/nvgpu/gp106/hal_gp106.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gp106/hal_gp106.c')
-rw-r--r--drivers/gpu/nvgpu/gp106/hal_gp106.c776
1 files changed, 776 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
new file mode 100644
index 00000000..e9ee77fc
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -0,0 +1,776 @@
1/*
2 * GP106 HAL interface
3 *
4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include "gk20a/gk20a.h"
26#include "gk20a/fifo_gk20a.h"
27#include "gk20a/fecs_trace_gk20a.h"
28#include "gk20a/mm_gk20a.h"
29#include "gk20a/dbg_gpu_gk20a.h"
30#include "gk20a/css_gr_gk20a.h"
31#include "gk20a/bus_gk20a.h"
32#include "gk20a/pramin_gk20a.h"
33#include "gk20a/flcn_gk20a.h"
34#include "gk20a/regops_gk20a.h"
35#include "gk20a/mc_gk20a.h"
36#include "gk20a/fb_gk20a.h"
37#include "gk20a/pmu_gk20a.h"
38#include "gk20a/gr_gk20a.h"
39
40#include "gp10b/ltc_gp10b.h"
41#include "gp10b/gr_gp10b.h"
42#include "gp10b/fecs_trace_gp10b.h"
43#include "gp10b/mc_gp10b.h"
44#include "gp10b/mm_gp10b.h"
45#include "gp10b/ce_gp10b.h"
46#include "gp10b/regops_gp10b.h"
47#include "gp10b/priv_ring_gp10b.h"
48#include "gp10b/fifo_gp10b.h"
49#include "gp10b/fb_gp10b.h"
50#include "gp10b/pmu_gp10b.h"
51#include "gp10b/gr_gp10b.h"
52
53#include "gp106/fifo_gp106.h"
54#include "gp106/regops_gp106.h"
55
56#include "gm20b/ltc_gm20b.h"
57#include "gm20b/gr_gm20b.h"
58#include "gm20b/fifo_gm20b.h"
59#include "gm20b/mm_gm20b.h"
60#include "gm20b/pmu_gm20b.h"
61#include "gm20b/fb_gm20b.h"
62#include "gm20b/acr_gm20b.h"
63#include "gm20b/gr_gm20b.h"
64
65#include "gp106/acr_gp106.h"
66#include "gp106/sec2_gp106.h"
67#include "gp106/clk_gp106.h"
68#include "gp106/clk_arb_gp106.h"
69#include "gp106/mclk_gp106.h"
70#include "gp106/bios_gp106.h"
71#include "gp106/therm_gp106.h"
72#include "gp106/xve_gp106.h"
73#include "gp106/fifo_gp106.h"
74#include "gp106/clk_gp106.h"
75#include "gp106/mm_gp106.h"
76#include "gp106/pmu_gp106.h"
77#include "gp106/gr_ctx_gp106.h"
78#include "gp106/gr_gp106.h"
79#include "gp106/fb_gp106.h"
80#include "gp106/gp106_gating_reglist.h"
81#include "gp106/flcn_gp106.h"
82
83#include "hal_gp106.h"
84
85#include <nvgpu/debug.h>
86#include <nvgpu/bug.h>
87#include <nvgpu/bus.h>
88#include <nvgpu/enabled.h>
89#include <nvgpu/ctxsw_trace.h>
90
91#include <nvgpu/hw/gp106/hw_proj_gp106.h>
92#include <nvgpu/hw/gp106/hw_fifo_gp106.h>
93#include <nvgpu/hw/gp106/hw_ram_gp106.h>
94#include <nvgpu/hw/gp106/hw_top_gp106.h>
95#include <nvgpu/hw/gp106/hw_pram_gp106.h>
96#include <nvgpu/hw/gp106/hw_pwr_gp106.h>
97
98
99static int gp106_get_litter_value(struct gk20a *g, int value)
100{
101 int ret = -EINVAL;
102
103 switch (value) {
104 case GPU_LIT_NUM_GPCS:
105 ret = proj_scal_litter_num_gpcs_v();
106 break;
107 case GPU_LIT_NUM_PES_PER_GPC:
108 ret = proj_scal_litter_num_pes_per_gpc_v();
109 break;
110 case GPU_LIT_NUM_SM_PER_TPC:
111 ret = proj_scal_litter_num_sm_per_tpc_v();
112 break;
113 case GPU_LIT_NUM_ZCULL_BANKS:
114 ret = proj_scal_litter_num_zcull_banks_v();
115 break;
116 case GPU_LIT_NUM_TPC_PER_GPC:
117 ret = proj_scal_litter_num_tpc_per_gpc_v();
118 break;
119 case GPU_LIT_NUM_FBPS:
120 ret = proj_scal_litter_num_fbps_v();
121 break;
122 case GPU_LIT_GPC_BASE:
123 ret = proj_gpc_base_v();
124 break;
125 case GPU_LIT_GPC_STRIDE:
126 ret = proj_gpc_stride_v();
127 break;
128 case GPU_LIT_GPC_SHARED_BASE:
129 ret = proj_gpc_shared_base_v();
130 break;
131 case GPU_LIT_TPC_IN_GPC_BASE:
132 ret = proj_tpc_in_gpc_base_v();
133 break;
134 case GPU_LIT_TPC_IN_GPC_STRIDE:
135 ret = proj_tpc_in_gpc_stride_v();
136 break;
137 case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
138 ret = proj_tpc_in_gpc_shared_base_v();
139 break;
140 case GPU_LIT_PPC_IN_GPC_BASE:
141 ret = proj_ppc_in_gpc_base_v();
142 break;
143 case GPU_LIT_PPC_IN_GPC_STRIDE:
144 ret = proj_ppc_in_gpc_stride_v();
145 break;
146 case GPU_LIT_PPC_IN_GPC_SHARED_BASE:
147 ret = proj_ppc_in_gpc_shared_base_v();
148 break;
149 case GPU_LIT_ROP_BASE:
150 ret = proj_rop_base_v();
151 break;
152 case GPU_LIT_ROP_STRIDE:
153 ret = proj_rop_stride_v();
154 break;
155 case GPU_LIT_ROP_SHARED_BASE:
156 ret = proj_rop_shared_base_v();
157 break;
158 case GPU_LIT_HOST_NUM_ENGINES:
159 ret = proj_host_num_engines_v();
160 break;
161 case GPU_LIT_HOST_NUM_PBDMA:
162 ret = proj_host_num_pbdma_v();
163 break;
164 case GPU_LIT_LTC_STRIDE:
165 ret = proj_ltc_stride_v();
166 break;
167 case GPU_LIT_LTS_STRIDE:
168 ret = proj_lts_stride_v();
169 break;
170 case GPU_LIT_NUM_FBPAS:
171 ret = proj_scal_litter_num_fbpas_v();
172 break;
173 case GPU_LIT_FBPA_SHARED_BASE:
174 ret = proj_fbpa_shared_base_v();
175 break;
176 case GPU_LIT_FBPA_BASE:
177 ret = proj_fbpa_base_v();
178 break;
179 case GPU_LIT_FBPA_STRIDE:
180 ret = proj_fbpa_stride_v();
181 break;
182 case GPU_LIT_TWOD_CLASS:
183 ret = FERMI_TWOD_A;
184 break;
185 case GPU_LIT_THREED_CLASS:
186 ret = PASCAL_B;
187 break;
188 case GPU_LIT_COMPUTE_CLASS:
189 ret = PASCAL_COMPUTE_B;
190 break;
191 case GPU_LIT_GPFIFO_CLASS:
192 ret = PASCAL_CHANNEL_GPFIFO_A;
193 break;
194 case GPU_LIT_I2M_CLASS:
195 ret = KEPLER_INLINE_TO_MEMORY_B;
196 break;
197 case GPU_LIT_DMA_COPY_CLASS:
198 ret = PASCAL_DMA_COPY_A;
199 break;
200 default:
201 BUG();
202 break;
203 }
204
205 return ret;
206}
207
208static int gp106_init_gpu_characteristics(struct gk20a *g)
209{
210 int err;
211
212 err = gk20a_init_gpu_characteristics(g);
213 if (err)
214 return err;
215
216 __nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_VOLTAGE, true);
217 __nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_CURRENT, true);
218 __nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_POWER, true);
219 __nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_TEMPERATURE, true);
220 __nvgpu_set_enabled(g, NVGPU_SUPPORT_DEVICE_EVENTS, true);
221 __nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_THERM_ALERT_LIMIT, true);
222
223 return 0;
224}
225
226static const struct gpu_ops gp106_ops = {
227 .bios = {
228 .init = gp106_bios_init,
229 .preos_wait_for_halt = gp106_bios_preos_wait_for_halt,
230 },
231 .ltc = {
232 .determine_L2_size_bytes = gp10b_determine_L2_size_bytes,
233 .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
234 .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
235 .init_cbc = NULL,
236 .init_fs_state = gm20b_ltc_init_fs_state,
237 .init_comptags = gp10b_ltc_init_comptags,
238 .cbc_ctrl = gm20b_ltc_cbc_ctrl,
239 .isr = gp10b_ltc_isr,
240 .cbc_fix_config = NULL,
241 .flush = gm20b_flush_ltc,
242 .set_enabled = gp10b_ltc_set_enabled,
243 },
244 .ce2 = {
245 .isr_stall = gp10b_ce_isr,
246 .isr_nonstall = gp10b_ce_nonstall_isr,
247 },
248 .gr = {
249 .get_patch_slots = gr_gk20a_get_patch_slots,
250 .init_gpc_mmu = gr_gm20b_init_gpc_mmu,
251 .bundle_cb_defaults = gr_gm20b_bundle_cb_defaults,
252 .cb_size_default = gr_gp106_cb_size_default,
253 .calc_global_ctx_buffer_size =
254 gr_gp10b_calc_global_ctx_buffer_size,
255 .commit_global_attrib_cb = gr_gp10b_commit_global_attrib_cb,
256 .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb,
257 .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager,
258 .commit_global_pagepool = gr_gp10b_commit_global_pagepool,
259 .handle_sw_method = gr_gp106_handle_sw_method,
260 .set_alpha_circular_buffer_size =
261 gr_gp10b_set_alpha_circular_buffer_size,
262 .set_circular_buffer_size = gr_gp10b_set_circular_buffer_size,
263 .enable_hww_exceptions = gr_gk20a_enable_hww_exceptions,
264 .is_valid_class = gr_gp106_is_valid_class,
265 .is_valid_gfx_class = gr_gp10b_is_valid_gfx_class,
266 .is_valid_compute_class = gr_gp10b_is_valid_compute_class,
267 .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs,
268 .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs,
269 .init_fs_state = gr_gp10b_init_fs_state,
270 .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask,
271 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
272 .set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask,
273 .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask,
274 .free_channel_ctx = gk20a_free_channel_ctx,
275 .alloc_obj_ctx = gk20a_alloc_obj_ctx,
276 .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull,
277 .get_zcull_info = gr_gk20a_get_zcull_info,
278 .is_tpc_addr = gr_gm20b_is_tpc_addr,
279 .get_tpc_num = gr_gm20b_get_tpc_num,
280 .detect_sm_arch = gr_gm20b_detect_sm_arch,
281 .add_zbc_color = gr_gp10b_add_zbc_color,
282 .add_zbc_depth = gr_gp10b_add_zbc_depth,
283 .zbc_set_table = gk20a_gr_zbc_set_table,
284 .zbc_query_table = gr_gk20a_query_zbc,
285 .pmu_save_zbc = gk20a_pmu_save_zbc,
286 .add_zbc = gr_gk20a_add_zbc,
287 .pagepool_default_size = gr_gp106_pagepool_default_size,
288 .init_ctx_state = gr_gp10b_init_ctx_state,
289 .alloc_gr_ctx = gr_gp10b_alloc_gr_ctx,
290 .free_gr_ctx = gr_gp10b_free_gr_ctx,
291 .update_ctxsw_preemption_mode =
292 gr_gp10b_update_ctxsw_preemption_mode,
293 .dump_gr_regs = gr_gp10b_dump_gr_status_regs,
294 .update_pc_sampling = gr_gm20b_update_pc_sampling,
295 .get_fbp_en_mask = gr_gm20b_get_fbp_en_mask,
296 .get_max_ltc_per_fbp = gr_gm20b_get_max_ltc_per_fbp,
297 .get_max_lts_per_ltc = gr_gm20b_get_max_lts_per_ltc,
298 .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask,
299 .get_max_fbps_count = gr_gm20b_get_max_fbps_count,
300 .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info,
301 .wait_empty = gr_gp10b_wait_empty,
302 .init_cyclestats = gr_gm20b_init_cyclestats,
303 .set_sm_debug_mode = gr_gk20a_set_sm_debug_mode,
304 .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
305 .bpt_reg_info = gr_gm20b_bpt_reg_info,
306 .get_access_map = gr_gp10b_get_access_map,
307 .handle_fecs_error = gr_gp10b_handle_fecs_error,
308 .handle_sm_exception = gr_gp10b_handle_sm_exception,
309 .handle_tex_exception = gr_gp10b_handle_tex_exception,
310 .enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions,
311 .enable_exceptions = gk20a_gr_enable_exceptions,
312 .get_lrf_tex_ltc_dram_override = get_ecc_override_val,
313 .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode,
314 .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode,
315 .record_sm_error_state = gm20b_gr_record_sm_error_state,
316 .update_sm_error_state = gm20b_gr_update_sm_error_state,
317 .clear_sm_error_state = gm20b_gr_clear_sm_error_state,
318 .suspend_contexts = gr_gp10b_suspend_contexts,
319 .resume_contexts = gr_gk20a_resume_contexts,
320 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
321 .init_sm_id_table = gr_gk20a_init_sm_id_table,
322 .load_smid_config = gr_gp10b_load_smid_config,
323 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
324 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
325 .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
326 .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
327 .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
328 .setup_rop_mapping = gr_gk20a_setup_rop_mapping,
329 .program_zcull_mapping = gr_gk20a_program_zcull_mapping,
330 .commit_global_timeslice = gr_gk20a_commit_global_timeslice,
331 .commit_inst = gr_gk20a_commit_inst,
332 .write_zcull_ptr = gr_gk20a_write_zcull_ptr,
333 .write_pm_ptr = gr_gk20a_write_pm_ptr,
334 .init_elcg_mode = gr_gk20a_init_elcg_mode,
335 .load_tpc_mask = gr_gm20b_load_tpc_mask,
336 .inval_icache = gr_gk20a_inval_icache,
337 .trigger_suspend = gr_gk20a_trigger_suspend,
338 .wait_for_pause = gr_gk20a_wait_for_pause,
339 .resume_from_pause = gr_gk20a_resume_from_pause,
340 .clear_sm_errors = gr_gk20a_clear_sm_errors,
341 .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions,
342 .get_esr_sm_sel = gk20a_gr_get_esr_sm_sel,
343 .sm_debugger_attached = gk20a_gr_sm_debugger_attached,
344 .suspend_single_sm = gk20a_gr_suspend_single_sm,
345 .suspend_all_sms = gk20a_gr_suspend_all_sms,
346 .resume_single_sm = gk20a_gr_resume_single_sm,
347 .resume_all_sms = gk20a_gr_resume_all_sms,
348 .get_sm_hww_warp_esr = gp10b_gr_get_sm_hww_warp_esr,
349 .get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr,
350 .get_sm_no_lock_down_hww_global_esr_mask =
351 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask,
352 .lock_down_sm = gk20a_gr_lock_down_sm,
353 .wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down,
354 .clear_sm_hww = gm20b_gr_clear_sm_hww,
355 .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf,
356 .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs,
357 .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
358 .set_boosted_ctx = NULL,
359 .set_preemption_mode = gr_gp10b_set_preemption_mode,
360 .set_czf_bypass = gr_gp10b_set_czf_bypass,
361 .init_czf_bypass = gr_gp10b_init_czf_bypass,
362 .pre_process_sm_exception = gr_gp10b_pre_process_sm_exception,
363 .set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va,
364 .init_preemption_state = NULL,
365 .update_boosted_ctx = NULL,
366 .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3,
367 .create_gr_sysfs = NULL,
368 .set_ctxsw_preemption_mode = gr_gp106_set_ctxsw_preemption_mode,
369 .load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode
370 },
371 .fb = {
372 .reset = gp106_fb_reset,
373 .init_hw = gk20a_fb_init_hw,
374 .init_fs_state = NULL,
375 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
376 .set_use_full_comp_tag_line =
377 gm20b_fb_set_use_full_comp_tag_line,
378 .compression_page_size = gp10b_fb_compression_page_size,
379 .compressible_page_size = gp10b_fb_compressible_page_size,
380 .vpr_info_fetch = gm20b_fb_vpr_info_fetch,
381 .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info,
382 .read_wpr_info = gm20b_fb_read_wpr_info,
383 .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled,
384 .set_debug_mode = gm20b_fb_set_debug_mode,
385 .tlb_invalidate = gk20a_fb_tlb_invalidate,
386 .mem_unlock = NULL,
387 },
388 .clock_gating = {
389 .slcg_bus_load_gating_prod =
390 gp106_slcg_bus_load_gating_prod,
391 .slcg_ce2_load_gating_prod =
392 gp106_slcg_ce2_load_gating_prod,
393 .slcg_chiplet_load_gating_prod =
394 gp106_slcg_chiplet_load_gating_prod,
395 .slcg_ctxsw_firmware_load_gating_prod =
396 gp106_slcg_ctxsw_firmware_load_gating_prod,
397 .slcg_fb_load_gating_prod =
398 gp106_slcg_fb_load_gating_prod,
399 .slcg_fifo_load_gating_prod =
400 gp106_slcg_fifo_load_gating_prod,
401 .slcg_gr_load_gating_prod =
402 gr_gp106_slcg_gr_load_gating_prod,
403 .slcg_ltc_load_gating_prod =
404 ltc_gp106_slcg_ltc_load_gating_prod,
405 .slcg_perf_load_gating_prod =
406 gp106_slcg_perf_load_gating_prod,
407 .slcg_priring_load_gating_prod =
408 gp106_slcg_priring_load_gating_prod,
409 .slcg_pmu_load_gating_prod =
410 gp106_slcg_pmu_load_gating_prod,
411 .slcg_therm_load_gating_prod =
412 gp106_slcg_therm_load_gating_prod,
413 .slcg_xbar_load_gating_prod =
414 gp106_slcg_xbar_load_gating_prod,
415 .blcg_bus_load_gating_prod =
416 gp106_blcg_bus_load_gating_prod,
417 .blcg_ce_load_gating_prod =
418 gp106_blcg_ce_load_gating_prod,
419 .blcg_fb_load_gating_prod =
420 gp106_blcg_fb_load_gating_prod,
421 .blcg_fifo_load_gating_prod =
422 gp106_blcg_fifo_load_gating_prod,
423 .blcg_gr_load_gating_prod =
424 gp106_blcg_gr_load_gating_prod,
425 .blcg_ltc_load_gating_prod =
426 gp106_blcg_ltc_load_gating_prod,
427 .blcg_pmu_load_gating_prod =
428 gp106_blcg_pmu_load_gating_prod,
429 .blcg_xbar_load_gating_prod =
430 gp106_blcg_xbar_load_gating_prod,
431 .pg_gr_load_gating_prod =
432 gr_gp106_pg_gr_load_gating_prod,
433 },
434 .fifo = {
435 .init_fifo_setup_hw = gk20a_init_fifo_setup_hw,
436 .bind_channel = channel_gm20b_bind,
437 .unbind_channel = gk20a_fifo_channel_unbind,
438 .disable_channel = gk20a_fifo_disable_channel,
439 .enable_channel = gk20a_fifo_enable_channel,
440 .alloc_inst = gk20a_fifo_alloc_inst,
441 .free_inst = gk20a_fifo_free_inst,
442 .setup_ramfc = channel_gp10b_setup_ramfc,
443 .channel_set_timeslice = gk20a_fifo_set_timeslice,
444 .default_timeslice_us = gk20a_fifo_default_timeslice_us,
445 .setup_userd = gk20a_fifo_setup_userd,
446 .userd_gp_get = gk20a_fifo_userd_gp_get,
447 .userd_gp_put = gk20a_fifo_userd_gp_put,
448 .userd_pb_get = gk20a_fifo_userd_pb_get,
449 .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
450 .preempt_channel = gk20a_fifo_preempt_channel,
451 .preempt_tsg = gk20a_fifo_preempt_tsg,
452 .enable_tsg = gk20a_enable_tsg,
453 .disable_tsg = gk20a_disable_tsg,
454 .tsg_verify_channel_status = gk20a_fifo_tsg_unbind_channel_verify_status,
455 .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload,
456 .update_runlist = gk20a_fifo_update_runlist,
457 .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault,
458 .get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info,
459 .wait_engine_idle = gk20a_fifo_wait_engine_idle,
460 .get_num_fifos = gp106_fifo_get_num_fifos,
461 .get_pbdma_signature = gp10b_fifo_get_pbdma_signature,
462 .set_runlist_interleave = gk20a_fifo_set_runlist_interleave,
463 .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice,
464 .force_reset_ch = gk20a_fifo_force_reset_ch,
465 .engine_enum_from_type = gp10b_fifo_engine_enum_from_type,
466 .device_info_data_parse = gp10b_device_info_data_parse,
467 .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v,
468 .init_engine_info = gk20a_fifo_init_engine_info,
469 .runlist_entry_size = ram_rl_entry_size_v,
470 .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry,
471 .get_ch_runlist_entry = gk20a_get_ch_runlist_entry,
472 .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc,
473 .dump_pbdma_status = gk20a_dump_pbdma_status,
474 .dump_eng_status = gk20a_dump_eng_status,
475 .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc,
476 .intr_0_error_mask = gk20a_fifo_intr_0_error_mask,
477 .is_preempt_pending = gk20a_fifo_is_preempt_pending,
478 .init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs,
479 .reset_enable_hw = gk20a_init_fifo_reset_enable_hw,
480 .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg,
481 .handle_sched_error = gk20a_fifo_handle_sched_error,
482 .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0,
483 .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1,
484 .tsg_bind_channel = gk20a_tsg_bind_channel,
485 .tsg_unbind_channel = gk20a_tsg_unbind_channel,
486#ifdef CONFIG_TEGRA_GK20A_NVHOST
487 .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
488 .free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
489 .add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd,
490 .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size,
491 .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd,
492 .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size,
493#endif
494 .resetup_ramfc = gp10b_fifo_resetup_ramfc,
495 .device_info_fault_id = top_device_info_data_fault_id_enum_v,
496 },
497 .gr_ctx = {
498 .get_netlist_name = gr_gp106_get_netlist_name,
499 .is_fw_defined = gr_gp106_is_firmware_defined,
500 },
501#ifdef CONFIG_GK20A_CTXSW_TRACE
502 .fecs_trace = {
503 .alloc_user_buffer = gk20a_ctxsw_dev_ring_alloc,
504 .free_user_buffer = gk20a_ctxsw_dev_ring_free,
505 .mmap_user_buffer = gk20a_ctxsw_dev_mmap_buffer,
506 .init = gk20a_fecs_trace_init,
507 .deinit = gk20a_fecs_trace_deinit,
508 .enable = gk20a_fecs_trace_enable,
509 .disable = gk20a_fecs_trace_disable,
510 .is_enabled = gk20a_fecs_trace_is_enabled,
511 .reset = gk20a_fecs_trace_reset,
512 .flush = gp10b_fecs_trace_flush,
513 .poll = gk20a_fecs_trace_poll,
514 .bind_channel = gk20a_fecs_trace_bind_channel,
515 .unbind_channel = gk20a_fecs_trace_unbind_channel,
516 .max_entries = gk20a_gr_max_entries,
517 },
518#endif /* CONFIG_GK20A_CTXSW_TRACE */
519 .mm = {
520 .support_sparse = gm20b_mm_support_sparse,
521 .gmmu_map = gk20a_locked_gmmu_map,
522 .gmmu_unmap = gk20a_locked_gmmu_unmap,
523 .vm_bind_channel = gk20a_vm_bind_channel,
524 .fb_flush = gk20a_mm_fb_flush,
525 .l2_invalidate = gk20a_mm_l2_invalidate,
526 .l2_flush = gk20a_mm_l2_flush,
527 .cbc_clean = gk20a_mm_cbc_clean,
528 .set_big_page_size = gm20b_mm_set_big_page_size,
529 .get_big_page_sizes = gm20b_mm_get_big_page_sizes,
530 .get_default_big_page_size = gp10b_mm_get_default_big_page_size,
531 .gpu_phys_addr = gm20b_gpu_phys_addr,
532 .get_mmu_levels = gp10b_mm_get_mmu_levels,
533 .init_pdb = gp10b_mm_init_pdb,
534 .init_mm_setup_hw = gp10b_init_mm_setup_hw,
535 .is_bar1_supported = gm20b_mm_is_bar1_supported,
536 .alloc_inst_block = gk20a_alloc_inst_block,
537 .init_inst_block = gk20a_init_inst_block,
538 .mmu_fault_pending = gk20a_fifo_mmu_fault_pending,
539 .init_bar2_vm = gb10b_init_bar2_vm,
540 .init_bar2_mm_hw_setup = gb10b_init_bar2_mm_hw_setup,
541 .remove_bar2_vm = gp10b_remove_bar2_vm,
542 .get_vidmem_size = gp106_mm_get_vidmem_size,
543 .get_kind_invalid = gm20b_get_kind_invalid,
544 .get_kind_pitch = gm20b_get_kind_pitch,
545 },
546 .pramin = {
547 .enter = gk20a_pramin_enter,
548 .exit = gk20a_pramin_exit,
549 .data032_r = pram_data032_r,
550 },
551 .therm = {
552#ifdef CONFIG_DEBUG_FS
553 .therm_debugfs_init = gp106_therm_debugfs_init,
554#endif /* CONFIG_DEBUG_FS */
555 .elcg_init_idle_filters = gp106_elcg_init_idle_filters,
556 .get_internal_sensor_curr_temp =
557 gp106_get_internal_sensor_curr_temp,
558 .get_internal_sensor_limits = gp106_get_internal_sensor_limits,
559 .configure_therm_alert = gp106_configure_therm_alert,
560 },
561 .pmu = {
562 .init_wpr_region = gm20b_pmu_init_acr,
563 .load_lsfalcon_ucode = gp106_load_falcon_ucode,
564 .is_lazy_bootstrap = gp106_is_lazy_bootstrap,
565 .is_priv_load = gp106_is_priv_load,
566 .prepare_ucode = gp106_prepare_ucode_blob,
567 .pmu_setup_hw_and_bootstrap = gp106_bootstrap_hs_flcn,
568 .get_wpr = gp106_wpr_info,
569 .alloc_blob_space = gp106_alloc_blob_space,
570 .pmu_populate_loader_cfg = gp106_pmu_populate_loader_cfg,
571 .flcn_populate_bl_dmem_desc = gp106_flcn_populate_bl_dmem_desc,
572 .falcon_wait_for_halt = sec2_wait_for_halt,
573 .falcon_clear_halt_interrupt_status =
574 sec2_clear_halt_interrupt_status,
575 .init_falcon_setup_hw = init_sec2_setup_hw1,
576 .pmu_queue_tail = gk20a_pmu_queue_tail,
577 .pmu_get_queue_head = pwr_pmu_queue_head_r,
578 .pmu_mutex_release = gk20a_pmu_mutex_release,
579 .is_pmu_supported = gp106_is_pmu_supported,
580 .pmu_pg_supported_engines_list = gp106_pmu_pg_engines_list,
581 .pmu_elpg_statistics = gp106_pmu_elpg_statistics,
582 .pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
583 .pmu_is_lpwr_feature_supported =
584 gp106_pmu_is_lpwr_feature_supported,
585 .pmu_msgq_tail = gk20a_pmu_msgq_tail,
586 .pmu_pg_engines_feature_list = gp106_pmu_pg_feature_list,
587 .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v,
588 .pmu_queue_head = gk20a_pmu_queue_head,
589 .pmu_pg_param_post_init = nvgpu_lpwr_post_init,
590 .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v,
591 .pmu_pg_init_param = gp106_pg_param_init,
592 .reset_engine = gp106_pmu_engine_reset,
593 .pmu_lpwr_disable_pg = nvgpu_lpwr_disable_pg,
594 .write_dmatrfbase = gp10b_write_dmatrfbase,
595 .pmu_mutex_size = pwr_pmu_mutex__size_1_v,
596 .is_engine_in_reset = gp106_pmu_is_engine_in_reset,
597 .pmu_get_queue_tail = pwr_pmu_queue_tail_r,
598 .pmu_lpwr_enable_pg = nvgpu_lpwr_enable_pg,
599 },
600 .clk = {
601 .init_clk_support = gp106_init_clk_support,
602 .get_crystal_clk_hz = gp106_crystal_clk_hz,
603 .measure_freq = gp106_clk_measure_freq,
604 .suspend_clk_support = gp106_suspend_clk_support,
605 .mclk_init = gp106_mclk_init,
606 .mclk_change = gp106_mclk_change,
607 .mclk_deinit = gp106_mclk_deinit,
608 },
609 .clk_arb = {
610 .get_arbiter_clk_domains = gp106_get_arbiter_clk_domains,
611 .get_arbiter_clk_range = gp106_get_arbiter_clk_range,
612 .get_arbiter_clk_default = gp106_get_arbiter_clk_default,
613 .get_current_pstate = nvgpu_clk_arb_get_current_pstate,
614 },
615 .regops = {
616 .get_global_whitelist_ranges =
617 gp106_get_global_whitelist_ranges,
618 .get_global_whitelist_ranges_count =
619 gp106_get_global_whitelist_ranges_count,
620 .get_context_whitelist_ranges =
621 gp106_get_context_whitelist_ranges,
622 .get_context_whitelist_ranges_count =
623 gp106_get_context_whitelist_ranges_count,
624 .get_runcontrol_whitelist = gp106_get_runcontrol_whitelist,
625 .get_runcontrol_whitelist_count =
626 gp106_get_runcontrol_whitelist_count,
627 .get_runcontrol_whitelist_ranges =
628 gp106_get_runcontrol_whitelist_ranges,
629 .get_runcontrol_whitelist_ranges_count =
630 gp106_get_runcontrol_whitelist_ranges_count,
631 .get_qctl_whitelist = gp106_get_qctl_whitelist,
632 .get_qctl_whitelist_count = gp106_get_qctl_whitelist_count,
633 .get_qctl_whitelist_ranges = gp106_get_qctl_whitelist_ranges,
634 .get_qctl_whitelist_ranges_count =
635 gp106_get_qctl_whitelist_ranges_count,
636 .apply_smpc_war = gp106_apply_smpc_war,
637 },
638 .mc = {
639 .intr_enable = mc_gp10b_intr_enable,
640 .intr_unit_config = mc_gp10b_intr_unit_config,
641 .isr_stall = mc_gp10b_isr_stall,
642 .intr_stall = mc_gp10b_intr_stall,
643 .intr_stall_pause = mc_gp10b_intr_stall_pause,
644 .intr_stall_resume = mc_gp10b_intr_stall_resume,
645 .intr_nonstall = mc_gp10b_intr_nonstall,
646 .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause,
647 .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume,
648 .enable = gk20a_mc_enable,
649 .disable = gk20a_mc_disable,
650 .reset = gk20a_mc_reset,
651 .boot_0 = gk20a_mc_boot_0,
652 .is_intr1_pending = mc_gp10b_is_intr1_pending,
653 },
654 .debug = {
655 .show_dump = gk20a_debug_show_dump,
656 },
657 .dbg_session_ops = {
658 .exec_reg_ops = exec_regops_gk20a,
659 .dbg_set_powergate = dbg_set_powergate,
660 .check_and_set_global_reservation =
661 nvgpu_check_and_set_global_reservation,
662 .check_and_set_context_reservation =
663 nvgpu_check_and_set_context_reservation,
664 .release_profiler_reservation =
665 nvgpu_release_profiler_reservation,
666 .perfbuffer_enable = gk20a_perfbuf_enable_locked,
667 .perfbuffer_disable = gk20a_perfbuf_disable_locked,
668 },
669 .bus = {
670 .init_hw = gk20a_bus_init_hw,
671 .isr = gk20a_bus_isr,
672 .read_ptimer = gk20a_read_ptimer,
673 .get_timestamps_zipper = nvgpu_get_timestamps_zipper,
674 .bar1_bind = gk20a_bus_bar1_bind,
675 },
676#if defined(CONFIG_GK20A_CYCLE_STATS)
677 .css = {
678 .enable_snapshot = css_hw_enable_snapshot,
679 .disable_snapshot = css_hw_disable_snapshot,
680 .check_data_available = css_hw_check_data_available,
681 .set_handled_snapshots = css_hw_set_handled_snapshots,
682 .allocate_perfmon_ids = css_gr_allocate_perfmon_ids,
683 .release_perfmon_ids = css_gr_release_perfmon_ids,
684 },
685#endif
686 .xve = {
687 .get_speed = xve_get_speed_gp106,
688 .set_speed = xve_set_speed_gp106,
689 .available_speeds = xve_available_speeds_gp106,
690 .xve_readl = xve_xve_readl_gp106,
691 .xve_writel = xve_xve_writel_gp106,
692 .disable_aspm = xve_disable_aspm_gp106,
693 .reset_gpu = xve_reset_gpu_gp106,
694#if defined(CONFIG_PCI_MSI)
695 .rearm_msi = xve_rearm_msi_gp106,
696#endif
697 .enable_shadow_rom = xve_enable_shadow_rom_gp106,
698 .disable_shadow_rom = xve_disable_shadow_rom_gp106,
699 .get_link_control_status = xve_get_link_control_status,
700 },
701 .falcon = {
702 .falcon_hal_sw_init = gp106_falcon_hal_sw_init,
703 },
704 .priv_ring = {
705 .isr = gp10b_priv_ring_isr,
706 },
707 .get_litter_value = gp106_get_litter_value,
708 .chip_init_gpu_characteristics = gp106_init_gpu_characteristics,
709};
710
711int gp106_init_hal(struct gk20a *g)
712{
713 struct gpu_ops *gops = &g->ops;
714
715 gk20a_dbg_fn("");
716
717 gops->bios = gp106_ops.bios;
718 gops->ltc = gp106_ops.ltc;
719 gops->ce2 = gp106_ops.ce2;
720 gops->gr = gp106_ops.gr;
721 gops->fb = gp106_ops.fb;
722 gops->clock_gating = gp106_ops.clock_gating;
723 gops->fifo = gp106_ops.fifo;
724 gops->gr_ctx = gp106_ops.gr_ctx;
725#ifdef CONFIG_GK20A_CTXSW_TRACE
726 gops->fecs_trace = gp106_ops.fecs_trace;
727#endif
728 gops->mm = gp106_ops.mm;
729 gops->pramin = gp106_ops.pramin;
730 gops->therm = gp106_ops.therm;
731 gops->pmu = gp106_ops.pmu;
732 /*
733 * clk must be assigned member by member
734 * since some clk ops are assigned during probe prior to HAL init
735 */
736 gops->clk.init_clk_support = gp106_ops.clk.init_clk_support;
737 gops->clk.get_crystal_clk_hz = gp106_ops.clk.get_crystal_clk_hz;
738 gops->clk.measure_freq = gp106_ops.clk.measure_freq;
739 gops->clk.suspend_clk_support = gp106_ops.clk.suspend_clk_support;
740 gops->clk.mclk_init = gp106_ops.clk.mclk_init;
741 gops->clk.mclk_change = gp106_ops.clk.mclk_change;
742 gops->clk.mclk_deinit = gp106_ops.clk.mclk_deinit;
743
744 gops->clk_arb = gp106_ops.clk_arb;
745 gops->regops = gp106_ops.regops;
746 gops->mc = gp106_ops.mc;
747 gops->debug = gp106_ops.debug;
748 gops->dbg_session_ops = gp106_ops.dbg_session_ops;
749 gops->bus = gp106_ops.bus;
750#if defined(CONFIG_GK20A_CYCLE_STATS)
751 gops->css = gp106_ops.css;
752#endif
753 gops->xve = gp106_ops.xve;
754 gops->falcon = gp106_ops.falcon;
755 gops->priv_ring = gp106_ops.priv_ring;
756
757 /* Lone functions */
758 gops->get_litter_value = gp106_ops.get_litter_value;
759 gops->chip_init_gpu_characteristics =
760 gp106_ops.chip_init_gpu_characteristics;
761
762 __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
763 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
764 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
765 __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true);
766 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
767
768 g->pmu_lsf_pmu_wpr_init_done = 0;
769 g->bootstrap_owner = LSF_FALCON_ID_SEC2;
770
771 g->name = "gp10x";
772
773 gk20a_dbg_fn("done");
774
775 return 0;
776}
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-22 16:14:27 -0400