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path: root/drivers/gpu/nvgpu/gp106/hal_gp106.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gp106/hal_gp106.c')
-rw-r--r--drivers/gpu/nvgpu/gp106/hal_gp106.c259
1 files changed, 259 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
new file mode 100644
index 00000000..ee361953
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -0,0 +1,259 @@
1/*
2 * GP106 HAL interface
3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/types.h>
17#include <linux/printk.h>
18
19#include <linux/types.h>
20
21#include "gk20a/gk20a.h"
22
23#include "gp10b/gr_gp10b.h"
24#include "gp10b/mc_gp10b.h"
25#include "gp106/ltc_gp106.h"
26#include "gp10b/mm_gp10b.h"
27#include "gp10b/ce_gp10b.h"
28#include "gp106/fifo_gp106.h"
29#include "gp106/regops_gp106.h"
30#include "gp10b/cde_gp10b.h"
31#include "gp106/therm_gp106.h"
32#include "gp106/xve_gp106.h"
33
34#include "gp106/bios_gp106.h"
35
36#include "gm20b/gr_gm20b.h"
37#include "gm20b/fifo_gm20b.h"
38#include "gm20b/pmu_gm20b.h"
39#include "gp106/clk_gp106.h"
40#include "gp106/clk_arb_gp106.h"
41
42#include "gp106/mm_gp106.h"
43#include "gp106/pmu_gp106.h"
44#include "gp106/gr_ctx_gp106.h"
45#include "gp106/gr_gp106.h"
46#include "gp106/fb_gp106.h"
47#include "gp106/gp106_gating_reglist.h"
48#include "nvgpu_gpuid_t18x.h"
49#include "hw_proj_gp106.h"
50#include "gk20a/dbg_gpu_gk20a.h"
51#include "gk20a/css_gr_gk20a.h"
52
53static struct gpu_ops gp106_ops = {
54 .clock_gating = {
55 .slcg_bus_load_gating_prod =
56 gp106_slcg_bus_load_gating_prod,
57 .slcg_ce2_load_gating_prod =
58 gp106_slcg_ce2_load_gating_prod,
59 .slcg_chiplet_load_gating_prod =
60 gp106_slcg_chiplet_load_gating_prod,
61 .slcg_ctxsw_firmware_load_gating_prod =
62 gp106_slcg_ctxsw_firmware_load_gating_prod,
63 .slcg_fb_load_gating_prod =
64 gp106_slcg_fb_load_gating_prod,
65 .slcg_fifo_load_gating_prod =
66 gp106_slcg_fifo_load_gating_prod,
67 .slcg_gr_load_gating_prod =
68 gr_gp106_slcg_gr_load_gating_prod,
69 .slcg_ltc_load_gating_prod =
70 ltc_gp106_slcg_ltc_load_gating_prod,
71 .slcg_perf_load_gating_prod =
72 gp106_slcg_perf_load_gating_prod,
73 .slcg_priring_load_gating_prod =
74 gp106_slcg_priring_load_gating_prod,
75 .slcg_pmu_load_gating_prod =
76 gp106_slcg_pmu_load_gating_prod,
77 .slcg_therm_load_gating_prod =
78 gp106_slcg_therm_load_gating_prod,
79 .slcg_xbar_load_gating_prod =
80 gp106_slcg_xbar_load_gating_prod,
81 .blcg_bus_load_gating_prod =
82 gp106_blcg_bus_load_gating_prod,
83 .blcg_ce_load_gating_prod =
84 gp106_blcg_ce_load_gating_prod,
85 .blcg_fb_load_gating_prod =
86 gp106_blcg_fb_load_gating_prod,
87 .blcg_fifo_load_gating_prod =
88 gp106_blcg_fifo_load_gating_prod,
89 .blcg_gr_load_gating_prod =
90 gp106_blcg_gr_load_gating_prod,
91 .blcg_ltc_load_gating_prod =
92 gp106_blcg_ltc_load_gating_prod,
93 .blcg_pmu_load_gating_prod =
94 gp106_blcg_pmu_load_gating_prod,
95 .blcg_xbar_load_gating_prod =
96 gp106_blcg_xbar_load_gating_prod,
97 .pg_gr_load_gating_prod =
98 gr_gp106_pg_gr_load_gating_prod,
99 }
100};
101
102static int gp106_get_litter_value(struct gk20a *g, int value)
103{
104 int ret = -EINVAL;
105
106 switch (value) {
107 case GPU_LIT_NUM_GPCS:
108 ret = proj_scal_litter_num_gpcs_v();
109 break;
110 case GPU_LIT_NUM_PES_PER_GPC:
111 ret = proj_scal_litter_num_pes_per_gpc_v();
112 break;
113 case GPU_LIT_NUM_ZCULL_BANKS:
114 ret = proj_scal_litter_num_zcull_banks_v();
115 break;
116 case GPU_LIT_NUM_TPC_PER_GPC:
117 ret = proj_scal_litter_num_tpc_per_gpc_v();
118 break;
119 case GPU_LIT_NUM_FBPS:
120 ret = proj_scal_litter_num_fbps_v();
121 break;
122 case GPU_LIT_GPC_BASE:
123 ret = proj_gpc_base_v();
124 break;
125 case GPU_LIT_GPC_STRIDE:
126 ret = proj_gpc_stride_v();
127 break;
128 case GPU_LIT_GPC_SHARED_BASE:
129 ret = proj_gpc_shared_base_v();
130 break;
131 case GPU_LIT_TPC_IN_GPC_BASE:
132 ret = proj_tpc_in_gpc_base_v();
133 break;
134 case GPU_LIT_TPC_IN_GPC_STRIDE:
135 ret = proj_tpc_in_gpc_stride_v();
136 break;
137 case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
138 ret = proj_tpc_in_gpc_shared_base_v();
139 break;
140 case GPU_LIT_PPC_IN_GPC_BASE:
141 ret = proj_ppc_in_gpc_base_v();
142 break;
143 case GPU_LIT_PPC_IN_GPC_STRIDE:
144 ret = proj_ppc_in_gpc_stride_v();
145 break;
146 case GPU_LIT_PPC_IN_GPC_SHARED_BASE:
147 ret = proj_ppc_in_gpc_shared_base_v();
148 break;
149 case GPU_LIT_ROP_BASE:
150 ret = proj_rop_base_v();
151 break;
152 case GPU_LIT_ROP_STRIDE:
153 ret = proj_rop_stride_v();
154 break;
155 case GPU_LIT_ROP_SHARED_BASE:
156 ret = proj_rop_shared_base_v();
157 break;
158 case GPU_LIT_HOST_NUM_ENGINES:
159 ret = proj_host_num_engines_v();
160 break;
161 case GPU_LIT_HOST_NUM_PBDMA:
162 ret = proj_host_num_pbdma_v();
163 break;
164 case GPU_LIT_LTC_STRIDE:
165 ret = proj_ltc_stride_v();
166 break;
167 case GPU_LIT_LTS_STRIDE:
168 ret = proj_lts_stride_v();
169 break;
170 case GPU_LIT_NUM_FBPAS:
171 ret = proj_scal_litter_num_fbpas_v();
172 break;
173 case GPU_LIT_FBPA_SHARED_BASE:
174 ret = proj_fbpa_shared_base_v();
175 break;
176 case GPU_LIT_FBPA_BASE:
177 ret = proj_fbpa_base_v();
178 break;
179 case GPU_LIT_FBPA_STRIDE:
180 ret = proj_fbpa_stride_v();
181 break;
182 default:
183 BUG();
184 break;
185 }
186
187 return ret;
188}
189
190int gp106_init_gpu_characteristics(struct gk20a *g)
191{
192 struct nvgpu_gpu_characteristics *gpu = &g->gpu_characteristics;
193
194 int err;
195
196 err = gk20a_init_gpu_characteristics(g);
197 if (err)
198 return err;
199
200 gpu->flags |= NVGPU_GPU_FLAGS_SUPPORT_GET_VOLTAGE |
201 NVGPU_GPU_FLAGS_SUPPORT_GET_CURRENT |
202 NVGPU_GPU_FLAGS_SUPPORT_GET_POWER |
203 NVGPU_GPU_FLAGS_SUPPORT_GET_TEMPERATURE;
204
205 return 0;
206}
207
208int gp106_init_hal(struct gk20a *g)
209{
210 struct gpu_ops *gops = &g->ops;
211 struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
212
213 gk20a_dbg_fn("");
214
215 *gops = gp106_ops;
216
217 gops->privsecurity = 1;
218 gops->securegpccs = 1;
219 gops->pmupstate = true;
220 gp10b_init_mc(gops);
221 gp106_init_gr(gops);
222 gp106_init_ltc(gops);
223 gp106_init_fb(gops);
224 gp106_init_fifo(gops);
225 gp10b_init_ce(gops);
226 gp106_init_gr_ctx(gops);
227 gp106_init_mm(gops);
228 gp106_init_pmu_ops(gops);
229 gk20a_init_debug_ops(gops);
230 gk20a_init_dbg_session_ops(gops);
231 gp106_init_clk_ops(gops);
232 gp106_init_clk_arb_ops(gops);
233 gp106_init_regops(gops);
234 gp10b_init_cde_ops(gops);
235 gk20a_init_tsg_ops(gops);
236#if defined(CONFIG_GK20A_CYCLE_STATS)
237 gk20a_init_css_ops(gops);
238#endif
239 gp106_init_bios(gops);
240 gp106_init_therm_ops(gops);
241 gp106_init_xve_ops(gops);
242
243 gops->name = "gp10x";
244 gops->get_litter_value = gp106_get_litter_value;
245 gops->chip_init_gpu_characteristics = gp106_init_gpu_characteristics;
246 gops->gr_ctx.use_dma_for_fw_bootstrap = true;
247 gops->read_ptimer = gk20a_read_ptimer;
248
249 c->twod_class = FERMI_TWOD_A;
250 c->threed_class = PASCAL_B;
251 c->compute_class = PASCAL_COMPUTE_B;
252 c->gpfifo_class = PASCAL_CHANNEL_GPFIFO_A;
253 c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B;
254 c->dma_copy_class = PASCAL_DMA_COPY_A;
255
256 gk20a_dbg_fn("done");
257
258 return 0;
259}
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