diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/hal_gp106.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 227b22e6..763dab44 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -313,6 +313,10 @@ static const struct gpu_ops gp106_ops = { | |||
313 | .resetup_ramfc = gp10b_fifo_resetup_ramfc, | 313 | .resetup_ramfc = gp10b_fifo_resetup_ramfc, |
314 | .device_info_fault_id = top_device_info_data_fault_id_enum_v, | 314 | .device_info_fault_id = top_device_info_data_fault_id_enum_v, |
315 | }, | 315 | }, |
316 | .gr_ctx = { | ||
317 | .get_netlist_name = gr_gp106_get_netlist_name, | ||
318 | .is_fw_defined = gr_gp106_is_firmware_defined, | ||
319 | }, | ||
316 | .mc = { | 320 | .mc = { |
317 | .intr_enable = mc_gp10b_intr_enable, | 321 | .intr_enable = mc_gp10b_intr_enable, |
318 | .intr_unit_config = mc_gp10b_intr_unit_config, | 322 | .intr_unit_config = mc_gp10b_intr_unit_config, |
@@ -403,6 +407,7 @@ int gp106_init_hal(struct gk20a *g) | |||
403 | gops->ce2 = gp106_ops.ce2; | 407 | gops->ce2 = gp106_ops.ce2; |
404 | gops->clock_gating = gp106_ops.clock_gating; | 408 | gops->clock_gating = gp106_ops.clock_gating; |
405 | gops->fifo = gp106_ops.fifo; | 409 | gops->fifo = gp106_ops.fifo; |
410 | gops->gr_ctx = gp106_ops.gr_ctx; | ||
406 | gops->mc = gp106_ops.mc; | 411 | gops->mc = gp106_ops.mc; |
407 | gops->debug = gp106_ops.debug; | 412 | gops->debug = gp106_ops.debug; |
408 | gops->dbg_session_ops = gp106_ops.dbg_session_ops; | 413 | gops->dbg_session_ops = gp106_ops.dbg_session_ops; |
@@ -421,6 +426,7 @@ int gp106_init_hal(struct gk20a *g) | |||
421 | gp106_ops.chip_init_gpu_characteristics; | 426 | gp106_ops.chip_init_gpu_characteristics; |
422 | gops->bios_init = gp106_ops.bios_init; | 427 | gops->bios_init = gp106_ops.bios_init; |
423 | 428 | ||
429 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | ||
424 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | 430 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); |
425 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | 431 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); |
426 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); | 432 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); |
@@ -429,7 +435,6 @@ int gp106_init_hal(struct gk20a *g) | |||
429 | gp106_init_gr(g); | 435 | gp106_init_gr(g); |
430 | gp10b_init_fecs_trace_ops(gops); | 436 | gp10b_init_fecs_trace_ops(gops); |
431 | gp106_init_fb(gops); | 437 | gp106_init_fb(gops); |
432 | gp106_init_gr_ctx(gops); | ||
433 | gp106_init_mm(gops); | 438 | gp106_init_mm(gops); |
434 | gp106_init_pmu_ops(g); | 439 | gp106_init_pmu_ops(g); |
435 | gp106_init_clk_ops(gops); | 440 | gp106_init_clk_ops(gops); |
@@ -439,7 +444,6 @@ int gp106_init_hal(struct gk20a *g) | |||
439 | gp106_init_therm_ops(gops); | 444 | gp106_init_therm_ops(gops); |
440 | 445 | ||
441 | g->name = "gp10x"; | 446 | g->name = "gp10x"; |
442 | gops->gr_ctx.use_dma_for_fw_bootstrap = true; | ||
443 | 447 | ||
444 | c->twod_class = FERMI_TWOD_A; | 448 | c->twod_class = FERMI_TWOD_A; |
445 | c->threed_class = PASCAL_B; | 449 | c->threed_class = PASCAL_B; |