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Diffstat (limited to 'drivers/gpu/nvgpu/gp106/gr_gp106.c')
-rw-r--r--drivers/gpu/nvgpu/gp106/gr_gp106.c246
1 files changed, 246 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.c b/drivers/gpu/nvgpu/gp106/gr_gp106.c
new file mode 100644
index 00000000..fea337e7
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/gr_gp106.c
@@ -0,0 +1,246 @@
1/*
2 * GP106 GPU GR
3 *
4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include <uapi/linux/nvgpu.h>
26
27#include <nvgpu/dma.h>
28
29#include "gk20a/gk20a.h"
30#include "gk20a/gr_gk20a.h"
31#include "gm20b/gr_gm20b.h"
32#include "gp10b/gr_gp10b.h"
33
34#include "gr_gp106.h"
35
36#include <nvgpu/hw/gp106/hw_gr_gp106.h>
37
38bool gr_gp106_is_valid_class(struct gk20a *g, u32 class_num)
39{
40 bool valid = false;
41
42 switch (class_num) {
43 case PASCAL_COMPUTE_A:
44 case PASCAL_COMPUTE_B:
45 case PASCAL_A:
46 case PASCAL_B:
47 case PASCAL_DMA_COPY_A:
48 case PASCAL_DMA_COPY_B:
49 valid = true;
50 break;
51
52 case MAXWELL_COMPUTE_B:
53 case MAXWELL_B:
54 case FERMI_TWOD_A:
55 case KEPLER_DMA_COPY_A:
56 case MAXWELL_DMA_COPY_A:
57 valid = true;
58 break;
59
60 default:
61 break;
62 }
63 gk20a_dbg_info("class=0x%x valid=%d", class_num, valid);
64 return valid;
65}
66
67u32 gr_gp106_pagepool_default_size(struct gk20a *g)
68{
69 return gr_scc_pagepool_total_pages_hwmax_value_v();
70}
71
72static void gr_gp106_set_go_idle_timeout(struct gk20a *g, u32 data)
73{
74 gk20a_writel(g, gr_fe_go_idle_timeout_r(), data);
75}
76
77int gr_gp106_handle_sw_method(struct gk20a *g, u32 addr,
78 u32 class_num, u32 offset, u32 data)
79{
80 gk20a_dbg_fn("");
81
82 if (class_num == PASCAL_COMPUTE_B) {
83 switch (offset << 2) {
84 case NVC0C0_SET_SHADER_EXCEPTIONS:
85 gk20a_gr_set_shader_exceptions(g, data);
86 break;
87 case NVC0C0_SET_RD_COALESCE:
88 gr_gm20b_set_rd_coalesce(g, data);
89 break;
90 default:
91 goto fail;
92 }
93 }
94
95 if (class_num == PASCAL_B) {
96 switch (offset << 2) {
97 case NVC097_SET_SHADER_EXCEPTIONS:
98 gk20a_gr_set_shader_exceptions(g, data);
99 break;
100 case NVC097_SET_CIRCULAR_BUFFER_SIZE:
101 g->ops.gr.set_circular_buffer_size(g, data);
102 break;
103 case NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE:
104 g->ops.gr.set_alpha_circular_buffer_size(g, data);
105 break;
106 case NVC097_SET_GO_IDLE_TIMEOUT:
107 gr_gp106_set_go_idle_timeout(g, data);
108 break;
109 case NVC097_SET_RD_COALESCE:
110 gr_gm20b_set_rd_coalesce(g, data);
111 break;
112 case NVC097_SET_BES_CROP_DEBUG3:
113 g->ops.gr.set_bes_crop_debug3(g, data);
114 break;
115 default:
116 goto fail;
117 }
118 }
119 return 0;
120
121fail:
122 return -EINVAL;
123}
124
125void gr_gp106_cb_size_default(struct gk20a *g)
126{
127 struct gr_gk20a *gr = &g->gr;
128
129 if (!gr->attrib_cb_default_size)
130 gr->attrib_cb_default_size = 0x800;
131 gr->alpha_cb_default_size =
132 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v();
133}
134
135int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g,
136 struct gr_ctx_desc *gr_ctx,
137 struct vm_gk20a *vm, u32 class,
138 u32 graphics_preempt_mode,
139 u32 compute_preempt_mode)
140{
141 int err = 0;
142
143 if (class == PASCAL_B && g->gr.t18x.ctx_vars.force_preemption_gfxp)
144 graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP;
145
146 if (class == PASCAL_COMPUTE_B &&
147 g->gr.t18x.ctx_vars.force_preemption_cilp)
148 compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP;
149
150 /* check for invalid combinations */
151 if ((graphics_preempt_mode == 0) && (compute_preempt_mode == 0))
152 return -EINVAL;
153
154 if ((graphics_preempt_mode == NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP) &&
155 (compute_preempt_mode == NVGPU_PREEMPTION_MODE_COMPUTE_CILP))
156 return -EINVAL;
157
158 /* set preemption modes */
159 switch (graphics_preempt_mode) {
160 case NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP:
161 {
162 u32 spill_size =
163 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() *
164 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v();
165 u32 pagepool_size = g->ops.gr.pagepool_default_size(g) *
166 gr_scc_pagepool_total_pages_byte_granularity_v();
167 u32 betacb_size = g->gr.attrib_cb_default_size +
168 (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() -
169 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v());
170 u32 attrib_cb_size = (betacb_size + g->gr.alpha_cb_size) *
171 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() *
172 g->gr.max_tpc_count;
173 attrib_cb_size = ALIGN(attrib_cb_size, 128);
174
175 gk20a_dbg_info("gfxp context spill_size=%d", spill_size);
176 gk20a_dbg_info("gfxp context pagepool_size=%d", pagepool_size);
177 gk20a_dbg_info("gfxp context attrib_cb_size=%d",
178 attrib_cb_size);
179
180 err = gr_gp10b_alloc_buffer(vm,
181 g->gr.t18x.ctx_vars.preempt_image_size,
182 &gr_ctx->t18x.preempt_ctxsw_buffer);
183 if (err) {
184 nvgpu_err(g, "cannot allocate preempt buffer");
185 goto fail;
186 }
187
188 err = gr_gp10b_alloc_buffer(vm,
189 spill_size,
190 &gr_ctx->t18x.spill_ctxsw_buffer);
191 if (err) {
192 nvgpu_err(g, "cannot allocate spill buffer");
193 goto fail_free_preempt;
194 }
195
196 err = gr_gp10b_alloc_buffer(vm,
197 attrib_cb_size,
198 &gr_ctx->t18x.betacb_ctxsw_buffer);
199 if (err) {
200 nvgpu_err(g, "cannot allocate beta buffer");
201 goto fail_free_spill;
202 }
203
204 err = gr_gp10b_alloc_buffer(vm,
205 pagepool_size,
206 &gr_ctx->t18x.pagepool_ctxsw_buffer);
207 if (err) {
208 nvgpu_err(g, "cannot allocate page pool");
209 goto fail_free_betacb;
210 }
211
212 gr_ctx->graphics_preempt_mode = graphics_preempt_mode;
213 break;
214 }
215
216 case NVGPU_PREEMPTION_MODE_GRAPHICS_WFI:
217 gr_ctx->graphics_preempt_mode = graphics_preempt_mode;
218 break;
219
220 default:
221 break;
222 }
223
224 if (class == PASCAL_COMPUTE_B) {
225 switch (compute_preempt_mode) {
226 case NVGPU_PREEMPTION_MODE_COMPUTE_WFI:
227 case NVGPU_PREEMPTION_MODE_COMPUTE_CTA:
228 case NVGPU_PREEMPTION_MODE_COMPUTE_CILP:
229 gr_ctx->compute_preempt_mode = compute_preempt_mode;
230 break;
231 default:
232 break;
233 }
234 }
235
236 return 0;
237
238fail_free_betacb:
239 nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer);
240fail_free_spill:
241 nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer);
242fail_free_preempt:
243 nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer);
244fail:
245 return err;
246}
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-22 16:26:59 -0400