diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/gp106_gating_reglist.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/gp106_gating_reglist.c | 679 |
1 files changed, 679 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.c b/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.c new file mode 100644 index 00000000..169a1fee --- /dev/null +++ b/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.c | |||
@@ -0,0 +1,679 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | * | ||
22 | * This file is autogenerated. Do not edit. | ||
23 | */ | ||
24 | |||
25 | #ifndef __gp106_gating_reglist_h__ | ||
26 | #define __gp106_gating_reglist_h__ | ||
27 | |||
28 | #include "gp106_gating_reglist.h" | ||
29 | #include <nvgpu/enabled.h> | ||
30 | |||
31 | struct gating_desc { | ||
32 | u32 addr; | ||
33 | u32 prod; | ||
34 | u32 disable; | ||
35 | }; | ||
36 | /* slcg bus */ | ||
37 | static const struct gating_desc gp106_slcg_bus[] = { | ||
38 | {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, | ||
39 | }; | ||
40 | |||
41 | /* slcg ce2 */ | ||
42 | static const struct gating_desc gp106_slcg_ce2[] = { | ||
43 | {.addr = 0x00104204, .prod = 0x00000000, .disable = 0x000007fe}, | ||
44 | }; | ||
45 | |||
46 | /* slcg chiplet */ | ||
47 | static const struct gating_desc gp106_slcg_chiplet[] = { | ||
48 | {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
49 | {.addr = 0x0010c0fc, .prod = 0x00000000, .disable = 0x00000007}, | ||
50 | {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
51 | {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
52 | {.addr = 0x0010d0fc, .prod = 0x00000000, .disable = 0x00000007}, | ||
53 | {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, | ||
54 | }; | ||
55 | |||
56 | /* slcg fb */ | ||
57 | static const struct gating_desc gp106_slcg_fb[] = { | ||
58 | {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
59 | {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
60 | }; | ||
61 | |||
62 | /* slcg fifo */ | ||
63 | static const struct gating_desc gp106_slcg_fifo[] = { | ||
64 | {.addr = 0x000026ac, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
65 | }; | ||
66 | |||
67 | /* slcg gr */ | ||
68 | static const struct gating_desc gp106_slcg_gr[] = { | ||
69 | {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe}, | ||
70 | {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
71 | {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x03fffffe}, | ||
72 | {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, | ||
73 | {.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
74 | {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, | ||
75 | {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, | ||
76 | {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, | ||
77 | {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe}, | ||
78 | {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
79 | {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x03fffffe}, | ||
80 | {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, | ||
81 | {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
82 | {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, | ||
83 | {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x000003fe}, | ||
84 | {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, | ||
85 | {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
86 | {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, | ||
87 | {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
88 | {.addr = 0x00418c74, .prod = 0xffffff80, .disable = 0xfffffffe}, | ||
89 | {.addr = 0x00418cf4, .prod = 0xfffffff8, .disable = 0xfffffffe}, | ||
90 | {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, | ||
91 | {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, | ||
92 | {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, | ||
93 | {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, | ||
94 | {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
95 | {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x0000ffff}, | ||
96 | {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e}, | ||
97 | {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
98 | {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e}, | ||
99 | {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e}, | ||
100 | {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe}, | ||
101 | {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e}, | ||
102 | {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e}, | ||
103 | {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e}, | ||
104 | {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e}, | ||
105 | {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, | ||
106 | {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe}, | ||
107 | {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe}, | ||
108 | {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, | ||
109 | {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe}, | ||
110 | {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe}, | ||
111 | {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe}, | ||
112 | {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe}, | ||
113 | {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
114 | {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, | ||
115 | {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, | ||
116 | {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe}, | ||
117 | {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
118 | {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
119 | {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
120 | {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x0000ffff}, | ||
121 | }; | ||
122 | |||
123 | /* slcg ltc */ | ||
124 | static const struct gating_desc gp106_slcg_ltc[] = { | ||
125 | {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
126 | {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
127 | }; | ||
128 | |||
129 | /* slcg perf */ | ||
130 | static const struct gating_desc gp106_slcg_perf[] = { | ||
131 | {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000}, | ||
132 | {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000}, | ||
133 | {.addr = 0x001bc218, .prod = 0x000001ff, .disable = 0x00000000}, | ||
134 | {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000}, | ||
135 | {.addr = 0x001b8218, .prod = 0x000001ff, .disable = 0x00000000}, | ||
136 | {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000}, | ||
137 | }; | ||
138 | |||
139 | /* slcg PriRing */ | ||
140 | static const struct gating_desc gp106_slcg_priring[] = { | ||
141 | {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, | ||
142 | }; | ||
143 | |||
144 | /* slcg pmu */ | ||
145 | static const struct gating_desc gp106_slcg_pmu[] = { | ||
146 | {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
147 | {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe}, | ||
148 | {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, | ||
149 | }; | ||
150 | |||
151 | /* therm gr */ | ||
152 | static const struct gating_desc gp106_slcg_therm[] = { | ||
153 | {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, | ||
154 | }; | ||
155 | |||
156 | /* slcg Xbar */ | ||
157 | static const struct gating_desc gp106_slcg_xbar[] = { | ||
158 | {.addr = 0x0013c824, .prod = 0x00000000, .disable = 0x7ffffffe}, | ||
159 | {.addr = 0x0013dc08, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
160 | {.addr = 0x0013c924, .prod = 0x00000000, .disable = 0x7ffffffe}, | ||
161 | {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
162 | {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
163 | {.addr = 0x0013cc24, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
164 | }; | ||
165 | |||
166 | /* blcg bus */ | ||
167 | static const struct gating_desc gp106_blcg_bus[] = { | ||
168 | {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, | ||
169 | }; | ||
170 | |||
171 | /* blcg ce */ | ||
172 | static const struct gating_desc gp106_blcg_ce[] = { | ||
173 | {.addr = 0x00104200, .prod = 0x0000c242, .disable = 0x00000000}, | ||
174 | }; | ||
175 | |||
176 | /* blcg fb */ | ||
177 | static const struct gating_desc gp106_blcg_fb[] = { | ||
178 | {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, | ||
179 | {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, | ||
180 | {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, | ||
181 | {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, | ||
182 | {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, | ||
183 | }; | ||
184 | |||
185 | /* blcg fifo */ | ||
186 | static const struct gating_desc gp106_blcg_fifo[] = { | ||
187 | {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000}, | ||
188 | }; | ||
189 | |||
190 | /* blcg gr */ | ||
191 | static const struct gating_desc gp106_blcg_gr[] = { | ||
192 | {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, | ||
193 | {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, | ||
194 | {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, | ||
195 | {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, | ||
196 | {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, | ||
197 | {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, | ||
198 | {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, | ||
199 | {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, | ||
200 | {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, | ||
201 | {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
202 | {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, | ||
203 | {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, | ||
204 | {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, | ||
205 | {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, | ||
206 | {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, | ||
207 | {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, | ||
208 | {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, | ||
209 | {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, | ||
210 | {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, | ||
211 | {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
212 | {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
213 | {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
214 | {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, | ||
215 | {.addr = 0x00418e0c, .prod = 0x00008444, .disable = 0x00000000}, | ||
216 | {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, | ||
217 | {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, | ||
218 | {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, | ||
219 | {.addr = 0x00419a40, .prod = 0x0000c242, .disable = 0x00000000}, | ||
220 | {.addr = 0x00419a48, .prod = 0x0000c242, .disable = 0x00000000}, | ||
221 | {.addr = 0x00419a50, .prod = 0x0000c242, .disable = 0x00000000}, | ||
222 | {.addr = 0x00419a58, .prod = 0x0000c242, .disable = 0x00000000}, | ||
223 | {.addr = 0x00419a60, .prod = 0x0000c242, .disable = 0x00000000}, | ||
224 | {.addr = 0x00419a68, .prod = 0x0000c242, .disable = 0x00000000}, | ||
225 | {.addr = 0x00419a70, .prod = 0x0000c242, .disable = 0x00000000}, | ||
226 | {.addr = 0x00419a78, .prod = 0x0000c242, .disable = 0x00000000}, | ||
227 | {.addr = 0x00419a80, .prod = 0x0000c242, .disable = 0x00000000}, | ||
228 | {.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000}, | ||
229 | {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000}, | ||
230 | {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000}, | ||
231 | {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
232 | {.addr = 0x00419fd0, .prod = 0x0000c044, .disable = 0x00000000}, | ||
233 | {.addr = 0x00419fd8, .prod = 0x0000c046, .disable = 0x00000000}, | ||
234 | {.addr = 0x00419fe0, .prod = 0x0000c044, .disable = 0x00000000}, | ||
235 | {.addr = 0x00419fe8, .prod = 0x0000c042, .disable = 0x00000000}, | ||
236 | {.addr = 0x00419ff0, .prod = 0x0000c045, .disable = 0x00000000}, | ||
237 | {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000}, | ||
238 | {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000}, | ||
239 | {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, | ||
240 | {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, | ||
241 | {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
242 | {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, | ||
243 | {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, | ||
244 | {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, | ||
245 | }; | ||
246 | |||
247 | /* blcg ltc */ | ||
248 | static const struct gating_desc gp106_blcg_ltc[] = { | ||
249 | {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, | ||
250 | {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, | ||
251 | {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, | ||
252 | {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, | ||
253 | }; | ||
254 | |||
255 | /* blcg pmu */ | ||
256 | static const struct gating_desc gp106_blcg_pmu[] = { | ||
257 | {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, | ||
258 | }; | ||
259 | |||
260 | /* blcg Xbar */ | ||
261 | static const struct gating_desc gp106_blcg_xbar[] = { | ||
262 | {.addr = 0x0013c820, .prod = 0x0001004a, .disable = 0x00000000}, | ||
263 | {.addr = 0x0013dc04, .prod = 0x0001004a, .disable = 0x00000000}, | ||
264 | {.addr = 0x0013c920, .prod = 0x0000004a, .disable = 0x00000000}, | ||
265 | {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, | ||
266 | {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, | ||
267 | {.addr = 0x0013cc20, .prod = 0x00000042, .disable = 0x00000000}, | ||
268 | }; | ||
269 | |||
270 | /* pg gr */ | ||
271 | static const struct gating_desc gp106_pg_gr[] = { | ||
272 | }; | ||
273 | |||
274 | /* inline functions */ | ||
275 | void gp106_slcg_bus_load_gating_prod(struct gk20a *g, | ||
276 | bool prod) | ||
277 | { | ||
278 | u32 i; | ||
279 | u32 size = sizeof(gp106_slcg_bus) / sizeof(struct gating_desc); | ||
280 | |||
281 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
282 | return; | ||
283 | |||
284 | for (i = 0; i < size; i++) { | ||
285 | if (prod) | ||
286 | gk20a_writel(g, gp106_slcg_bus[i].addr, | ||
287 | gp106_slcg_bus[i].prod); | ||
288 | else | ||
289 | gk20a_writel(g, gp106_slcg_bus[i].addr, | ||
290 | gp106_slcg_bus[i].disable); | ||
291 | } | ||
292 | } | ||
293 | |||
294 | void gp106_slcg_ce2_load_gating_prod(struct gk20a *g, | ||
295 | bool prod) | ||
296 | { | ||
297 | u32 i; | ||
298 | u32 size = sizeof(gp106_slcg_ce2) / sizeof(struct gating_desc); | ||
299 | |||
300 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
301 | return; | ||
302 | |||
303 | for (i = 0; i < size; i++) { | ||
304 | if (prod) | ||
305 | gk20a_writel(g, gp106_slcg_ce2[i].addr, | ||
306 | gp106_slcg_ce2[i].prod); | ||
307 | else | ||
308 | gk20a_writel(g, gp106_slcg_ce2[i].addr, | ||
309 | gp106_slcg_ce2[i].disable); | ||
310 | } | ||
311 | } | ||
312 | |||
313 | void gp106_slcg_chiplet_load_gating_prod(struct gk20a *g, | ||
314 | bool prod) | ||
315 | { | ||
316 | u32 i; | ||
317 | u32 size = sizeof(gp106_slcg_chiplet) / sizeof(struct gating_desc); | ||
318 | |||
319 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
320 | return; | ||
321 | |||
322 | for (i = 0; i < size; i++) { | ||
323 | if (prod) | ||
324 | gk20a_writel(g, gp106_slcg_chiplet[i].addr, | ||
325 | gp106_slcg_chiplet[i].prod); | ||
326 | else | ||
327 | gk20a_writel(g, gp106_slcg_chiplet[i].addr, | ||
328 | gp106_slcg_chiplet[i].disable); | ||
329 | } | ||
330 | } | ||
331 | |||
332 | void gp106_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
333 | bool prod) | ||
334 | { | ||
335 | } | ||
336 | |||
337 | void gp106_slcg_fb_load_gating_prod(struct gk20a *g, | ||
338 | bool prod) | ||
339 | { | ||
340 | u32 i; | ||
341 | u32 size = sizeof(gp106_slcg_fb) / sizeof(struct gating_desc); | ||
342 | |||
343 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
344 | return; | ||
345 | |||
346 | for (i = 0; i < size; i++) { | ||
347 | if (prod) | ||
348 | gk20a_writel(g, gp106_slcg_fb[i].addr, | ||
349 | gp106_slcg_fb[i].prod); | ||
350 | else | ||
351 | gk20a_writel(g, gp106_slcg_fb[i].addr, | ||
352 | gp106_slcg_fb[i].disable); | ||
353 | } | ||
354 | } | ||
355 | |||
356 | void gp106_slcg_fifo_load_gating_prod(struct gk20a *g, | ||
357 | bool prod) | ||
358 | { | ||
359 | u32 i; | ||
360 | u32 size = sizeof(gp106_slcg_fifo) / sizeof(struct gating_desc); | ||
361 | |||
362 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
363 | return; | ||
364 | |||
365 | for (i = 0; i < size; i++) { | ||
366 | if (prod) | ||
367 | gk20a_writel(g, gp106_slcg_fifo[i].addr, | ||
368 | gp106_slcg_fifo[i].prod); | ||
369 | else | ||
370 | gk20a_writel(g, gp106_slcg_fifo[i].addr, | ||
371 | gp106_slcg_fifo[i].disable); | ||
372 | } | ||
373 | } | ||
374 | |||
375 | void gr_gp106_slcg_gr_load_gating_prod(struct gk20a *g, | ||
376 | bool prod) | ||
377 | { | ||
378 | u32 i; | ||
379 | u32 size = sizeof(gp106_slcg_gr) / sizeof(struct gating_desc); | ||
380 | |||
381 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
382 | return; | ||
383 | |||
384 | for (i = 0; i < size; i++) { | ||
385 | if (prod) | ||
386 | gk20a_writel(g, gp106_slcg_gr[i].addr, | ||
387 | gp106_slcg_gr[i].prod); | ||
388 | else | ||
389 | gk20a_writel(g, gp106_slcg_gr[i].addr, | ||
390 | gp106_slcg_gr[i].disable); | ||
391 | } | ||
392 | } | ||
393 | |||
394 | void ltc_gp106_slcg_ltc_load_gating_prod(struct gk20a *g, | ||
395 | bool prod) | ||
396 | { | ||
397 | u32 i; | ||
398 | u32 size = sizeof(gp106_slcg_ltc) / sizeof(struct gating_desc); | ||
399 | |||
400 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
401 | return; | ||
402 | |||
403 | for (i = 0; i < size; i++) { | ||
404 | if (prod) | ||
405 | gk20a_writel(g, gp106_slcg_ltc[i].addr, | ||
406 | gp106_slcg_ltc[i].prod); | ||
407 | else | ||
408 | gk20a_writel(g, gp106_slcg_ltc[i].addr, | ||
409 | gp106_slcg_ltc[i].disable); | ||
410 | } | ||
411 | } | ||
412 | |||
413 | void gp106_slcg_perf_load_gating_prod(struct gk20a *g, | ||
414 | bool prod) | ||
415 | { | ||
416 | u32 i; | ||
417 | u32 size = sizeof(gp106_slcg_perf) / sizeof(struct gating_desc); | ||
418 | |||
419 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
420 | return; | ||
421 | |||
422 | for (i = 0; i < size; i++) { | ||
423 | if (prod) | ||
424 | gk20a_writel(g, gp106_slcg_perf[i].addr, | ||
425 | gp106_slcg_perf[i].prod); | ||
426 | else | ||
427 | gk20a_writel(g, gp106_slcg_perf[i].addr, | ||
428 | gp106_slcg_perf[i].disable); | ||
429 | } | ||
430 | } | ||
431 | |||
432 | void gp106_slcg_priring_load_gating_prod(struct gk20a *g, | ||
433 | bool prod) | ||
434 | { | ||
435 | u32 i; | ||
436 | u32 size = sizeof(gp106_slcg_priring) / sizeof(struct gating_desc); | ||
437 | |||
438 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
439 | return; | ||
440 | |||
441 | for (i = 0; i < size; i++) { | ||
442 | if (prod) | ||
443 | gk20a_writel(g, gp106_slcg_priring[i].addr, | ||
444 | gp106_slcg_priring[i].prod); | ||
445 | else | ||
446 | gk20a_writel(g, gp106_slcg_priring[i].addr, | ||
447 | gp106_slcg_priring[i].disable); | ||
448 | } | ||
449 | } | ||
450 | |||
451 | void gp106_slcg_pmu_load_gating_prod(struct gk20a *g, | ||
452 | bool prod) | ||
453 | { | ||
454 | u32 i; | ||
455 | u32 size = sizeof(gp106_slcg_pmu) / sizeof(struct gating_desc); | ||
456 | |||
457 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
458 | return; | ||
459 | |||
460 | for (i = 0; i < size; i++) { | ||
461 | if (prod) | ||
462 | gk20a_writel(g, gp106_slcg_pmu[i].addr, | ||
463 | gp106_slcg_pmu[i].prod); | ||
464 | else | ||
465 | gk20a_writel(g, gp106_slcg_pmu[i].addr, | ||
466 | gp106_slcg_pmu[i].disable); | ||
467 | } | ||
468 | } | ||
469 | |||
470 | void gp106_slcg_therm_load_gating_prod(struct gk20a *g, | ||
471 | bool prod) | ||
472 | { | ||
473 | u32 i; | ||
474 | u32 size = sizeof(gp106_slcg_therm) / sizeof(struct gating_desc); | ||
475 | |||
476 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
477 | return; | ||
478 | |||
479 | for (i = 0; i < size; i++) { | ||
480 | if (prod) | ||
481 | gk20a_writel(g, gp106_slcg_therm[i].addr, | ||
482 | gp106_slcg_therm[i].prod); | ||
483 | else | ||
484 | gk20a_writel(g, gp106_slcg_therm[i].addr, | ||
485 | gp106_slcg_therm[i].disable); | ||
486 | } | ||
487 | } | ||
488 | |||
489 | void gp106_slcg_xbar_load_gating_prod(struct gk20a *g, | ||
490 | bool prod) | ||
491 | { | ||
492 | u32 i; | ||
493 | u32 size = sizeof(gp106_slcg_xbar) / sizeof(struct gating_desc); | ||
494 | |||
495 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
496 | return; | ||
497 | |||
498 | for (i = 0; i < size; i++) { | ||
499 | if (prod) | ||
500 | gk20a_writel(g, gp106_slcg_xbar[i].addr, | ||
501 | gp106_slcg_xbar[i].prod); | ||
502 | else | ||
503 | gk20a_writel(g, gp106_slcg_xbar[i].addr, | ||
504 | gp106_slcg_xbar[i].disable); | ||
505 | } | ||
506 | } | ||
507 | |||
508 | void gp106_blcg_bus_load_gating_prod(struct gk20a *g, | ||
509 | bool prod) | ||
510 | { | ||
511 | u32 i; | ||
512 | u32 size = sizeof(gp106_blcg_bus) / sizeof(struct gating_desc); | ||
513 | |||
514 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
515 | return; | ||
516 | |||
517 | for (i = 0; i < size; i++) { | ||
518 | if (prod) | ||
519 | gk20a_writel(g, gp106_blcg_bus[i].addr, | ||
520 | gp106_blcg_bus[i].prod); | ||
521 | else | ||
522 | gk20a_writel(g, gp106_blcg_bus[i].addr, | ||
523 | gp106_blcg_bus[i].disable); | ||
524 | } | ||
525 | } | ||
526 | |||
527 | void gp106_blcg_ce_load_gating_prod(struct gk20a *g, | ||
528 | bool prod) | ||
529 | { | ||
530 | u32 i; | ||
531 | u32 size = sizeof(gp106_blcg_ce) / sizeof(struct gating_desc); | ||
532 | |||
533 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
534 | return; | ||
535 | |||
536 | for (i = 0; i < size; i++) { | ||
537 | if (prod) | ||
538 | gk20a_writel(g, gp106_blcg_ce[i].addr, | ||
539 | gp106_blcg_ce[i].prod); | ||
540 | else | ||
541 | gk20a_writel(g, gp106_blcg_ce[i].addr, | ||
542 | gp106_blcg_ce[i].disable); | ||
543 | } | ||
544 | } | ||
545 | |||
546 | void gp106_blcg_fb_load_gating_prod(struct gk20a *g, | ||
547 | bool prod) | ||
548 | { | ||
549 | u32 i; | ||
550 | u32 size = sizeof(gp106_blcg_fb) / sizeof(struct gating_desc); | ||
551 | |||
552 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
553 | return; | ||
554 | |||
555 | for (i = 0; i < size; i++) { | ||
556 | if (prod) | ||
557 | gk20a_writel(g, gp106_blcg_fb[i].addr, | ||
558 | gp106_blcg_fb[i].prod); | ||
559 | else | ||
560 | gk20a_writel(g, gp106_blcg_fb[i].addr, | ||
561 | gp106_blcg_fb[i].disable); | ||
562 | } | ||
563 | } | ||
564 | |||
565 | void gp106_blcg_fifo_load_gating_prod(struct gk20a *g, | ||
566 | bool prod) | ||
567 | { | ||
568 | u32 i; | ||
569 | u32 size = sizeof(gp106_blcg_fifo) / sizeof(struct gating_desc); | ||
570 | |||
571 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
572 | return; | ||
573 | |||
574 | for (i = 0; i < size; i++) { | ||
575 | if (prod) | ||
576 | gk20a_writel(g, gp106_blcg_fifo[i].addr, | ||
577 | gp106_blcg_fifo[i].prod); | ||
578 | else | ||
579 | gk20a_writel(g, gp106_blcg_fifo[i].addr, | ||
580 | gp106_blcg_fifo[i].disable); | ||
581 | } | ||
582 | } | ||
583 | |||
584 | void gp106_blcg_gr_load_gating_prod(struct gk20a *g, | ||
585 | bool prod) | ||
586 | { | ||
587 | u32 i; | ||
588 | u32 size = sizeof(gp106_blcg_gr) / sizeof(struct gating_desc); | ||
589 | |||
590 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
591 | return; | ||
592 | |||
593 | for (i = 0; i < size; i++) { | ||
594 | if (prod) | ||
595 | gk20a_writel(g, gp106_blcg_gr[i].addr, | ||
596 | gp106_blcg_gr[i].prod); | ||
597 | else | ||
598 | gk20a_writel(g, gp106_blcg_gr[i].addr, | ||
599 | gp106_blcg_gr[i].disable); | ||
600 | } | ||
601 | } | ||
602 | |||
603 | void gp106_blcg_ltc_load_gating_prod(struct gk20a *g, | ||
604 | bool prod) | ||
605 | { | ||
606 | u32 i; | ||
607 | u32 size = sizeof(gp106_blcg_ltc) / sizeof(struct gating_desc); | ||
608 | |||
609 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
610 | return; | ||
611 | |||
612 | for (i = 0; i < size; i++) { | ||
613 | if (prod) | ||
614 | gk20a_writel(g, gp106_blcg_ltc[i].addr, | ||
615 | gp106_blcg_ltc[i].prod); | ||
616 | else | ||
617 | gk20a_writel(g, gp106_blcg_ltc[i].addr, | ||
618 | gp106_blcg_ltc[i].disable); | ||
619 | } | ||
620 | } | ||
621 | |||
622 | void gp106_blcg_pmu_load_gating_prod(struct gk20a *g, | ||
623 | bool prod) | ||
624 | { | ||
625 | u32 i; | ||
626 | u32 size = sizeof(gp106_blcg_pmu) / sizeof(struct gating_desc); | ||
627 | |||
628 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
629 | return; | ||
630 | |||
631 | for (i = 0; i < size; i++) { | ||
632 | if (prod) | ||
633 | gk20a_writel(g, gp106_blcg_pmu[i].addr, | ||
634 | gp106_blcg_pmu[i].prod); | ||
635 | else | ||
636 | gk20a_writel(g, gp106_blcg_pmu[i].addr, | ||
637 | gp106_blcg_pmu[i].disable); | ||
638 | } | ||
639 | } | ||
640 | |||
641 | void gp106_blcg_xbar_load_gating_prod(struct gk20a *g, | ||
642 | bool prod) | ||
643 | { | ||
644 | u32 i; | ||
645 | u32 size = sizeof(gp106_blcg_xbar) / sizeof(struct gating_desc); | ||
646 | |||
647 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
648 | return; | ||
649 | |||
650 | for (i = 0; i < size; i++) { | ||
651 | if (prod) | ||
652 | gk20a_writel(g, gp106_blcg_xbar[i].addr, | ||
653 | gp106_blcg_xbar[i].prod); | ||
654 | else | ||
655 | gk20a_writel(g, gp106_blcg_xbar[i].addr, | ||
656 | gp106_blcg_xbar[i].disable); | ||
657 | } | ||
658 | } | ||
659 | |||
660 | void gr_gp106_pg_gr_load_gating_prod(struct gk20a *g, | ||
661 | bool prod) | ||
662 | { | ||
663 | u32 i; | ||
664 | u32 size = sizeof(gp106_pg_gr) / sizeof(struct gating_desc); | ||
665 | |||
666 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
667 | return; | ||
668 | |||
669 | for (i = 0; i < size; i++) { | ||
670 | if (prod) | ||
671 | gk20a_writel(g, gp106_pg_gr[i].addr, | ||
672 | gp106_pg_gr[i].prod); | ||
673 | else | ||
674 | gk20a_writel(g, gp106_pg_gr[i].addr, | ||
675 | gp106_pg_gr[i].disable); | ||
676 | } | ||
677 | } | ||
678 | |||
679 | #endif /* __gp106_gating_reglist_h__ */ | ||