1 files changed, 94 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp106/flcn_gp106.c b/drivers/gpu/nvgpu/gp106/flcn_gp106.c
new file mode 100644
index 00000000..7949edb7
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/flcn_gp106.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#include "gk20a/gk20a.h"
+#include "gk20a/flcn_gk20a.h"
+#include "gp106/sec2_gp106.h"
+#include <nvgpu/hw/gp106/hw_falcon_gp106.h>
+static void gp106_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn)
+{
+        struct nvgpu_falcon_engine_dependency_ops *flcn_eng_dep_ops =
+                        &flcn->flcn_engine_dep_ops;
+        switch (flcn->flcn_id) {
+        case FALCON_ID_PMU:
+                flcn_eng_dep_ops->reset_eng = nvgpu_pmu_reset;
+                break;
+        case FALCON_ID_SEC2:
+                flcn_eng_dep_ops->reset_eng = gp106_sec2_reset;
+                break;
+        default:
+                flcn_eng_dep_ops->reset_eng = NULL;
+                break;
+        }
+}
+static void gp106_falcon_ops(struct nvgpu_falcon *flcn)
+{
+        gk20a_falcon_ops(flcn);
+        gp106_falcon_engine_dependency_ops(flcn);
+}
+void gp106_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
+{
+        struct gk20a *g = flcn->g;
+        switch (flcn->flcn_id) {
+        case FALCON_ID_PMU:
+                flcn->flcn_base = FALCON_PWR_BASE;
+                flcn->is_falcon_supported = true;
+                flcn->is_interrupt_enabled = true;
+                break;
+        case FALCON_ID_SEC2:
+                flcn->flcn_base = FALCON_SEC_BASE;
+                flcn->is_falcon_supported = true;
+                flcn->is_interrupt_enabled = false;
+                break;
+        case FALCON_ID_FECS:
+                flcn->flcn_base = FALCON_FECS_BASE;
+                flcn->is_falcon_supported = true;
+                flcn->is_interrupt_enabled = false;
+        break;
+        case FALCON_ID_GPCCS:
+                flcn->flcn_base = FALCON_GPCCS_BASE;
+                flcn->is_falcon_supported = true;
+                flcn->is_interrupt_enabled = false;
+        break;
+        case FALCON_ID_NVDEC:
+                flcn->flcn_base = FALCON_NVDEC_BASE;
+                flcn->is_falcon_supported = true;
+                flcn->is_interrupt_enabled = true;
+        break;
+        default:
+                flcn->is_falcon_supported = false;
+                nvgpu_err(g, "Invalid flcn request");
+                break;
+        }
+        if (flcn->is_falcon_supported) {
+                nvgpu_mutex_init(&flcn->copy_lock);
+                gp106_falcon_ops(flcn);
+        } else
+                nvgpu_info(g, "falcon 0x%x not supported on %s",
+                        flcn->flcn_id, g->name);
+}

diff --git a/drivers/gpu/nvgpu/gp106/flcn_gp106.c b/drivers/gpu/nvgpu/gp106/flcn_gp106.c new file mode 100644 index 00000000..7949edb7 --- /dev/null +++ b/drivers/gpu/nvgpu/gp106/flcn_gp106.c
@@ -0,0 +1,94 @@
	1	/*
	2	* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	18	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	19	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	20	* DEALINGS IN THE SOFTWARE.
	21	*/
	22	#include "gk20a/gk20a.h"
	23	#include "gk20a/flcn_gk20a.h"
	24	#include "gp106/sec2_gp106.h"
	25
	26	#include <nvgpu/hw/gp106/hw_falcon_gp106.h>
	27
	28	static void gp106_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn)
	29	{
	30	struct nvgpu_falcon_engine_dependency_ops *flcn_eng_dep_ops =
	31	&flcn->flcn_engine_dep_ops;
	32
	33	switch (flcn->flcn_id) {
	34	case FALCON_ID_PMU:
	35	flcn_eng_dep_ops->reset_eng = nvgpu_pmu_reset;
	36	break;
	37	case FALCON_ID_SEC2:
	38	flcn_eng_dep_ops->reset_eng = gp106_sec2_reset;
	39	break;
	40	default:
	41	flcn_eng_dep_ops->reset_eng = NULL;
	42	break;
	43	}
	44	}
	45
	46	static void gp106_falcon_ops(struct nvgpu_falcon *flcn)
	47	{
	48	gk20a_falcon_ops(flcn);
	49	gp106_falcon_engine_dependency_ops(flcn);
	50	}
	51
	52	void gp106_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
	53	{
	54	struct gk20a *g = flcn->g;
	55
	56	switch (flcn->flcn_id) {
	57	case FALCON_ID_PMU:
	58	flcn->flcn_base = FALCON_PWR_BASE;
	59	flcn->is_falcon_supported = true;
	60	flcn->is_interrupt_enabled = true;
	61	break;
	62	case FALCON_ID_SEC2:
	63	flcn->flcn_base = FALCON_SEC_BASE;
	64	flcn->is_falcon_supported = true;
	65	flcn->is_interrupt_enabled = false;
	66	break;
	67	case FALCON_ID_FECS:
	68	flcn->flcn_base = FALCON_FECS_BASE;
	69	flcn->is_falcon_supported = true;
	70	flcn->is_interrupt_enabled = false;
	71	break;
	72	case FALCON_ID_GPCCS:
	73	flcn->flcn_base = FALCON_GPCCS_BASE;
	74	flcn->is_falcon_supported = true;
	75	flcn->is_interrupt_enabled = false;
	76	break;
	77	case FALCON_ID_NVDEC:
	78	flcn->flcn_base = FALCON_NVDEC_BASE;
	79	flcn->is_falcon_supported = true;
	80	flcn->is_interrupt_enabled = true;
	81	break;
	82	default:
	83	flcn->is_falcon_supported = false;
	84	nvgpu_err(g, "Invalid flcn request");
	85	break;
	86	}
	87
	88	if (flcn->is_falcon_supported) {
	89	nvgpu_mutex_init(&flcn->copy_lock);
	90	gp106_falcon_ops(flcn);
	91	} else
	92	nvgpu_info(g, "falcon 0x%x not supported on %s",
	93	flcn->flcn_id, g->name);
	94	}