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path: root/drivers/gpu/nvgpu/gp106/clk_gp106.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gp106/clk_gp106.c')
-rw-r--r--drivers/gpu/nvgpu/gp106/clk_gp106.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.c b/drivers/gpu/nvgpu/gp106/clk_gp106.c
index edeb97ec..3b9c444d 100644
--- a/drivers/gpu/nvgpu/gp106/clk_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/clk_gp106.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GP106 Clocks 2 * GP106 Clocks
3 * 3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -79,7 +79,7 @@ static int gp106_init_clk_support(struct gk20a *g) {
79 79
80 gk20a_dbg_fn(""); 80 gk20a_dbg_fn("");
81 81
82 mutex_init(&clk->clk_mutex); 82 nvgpu_mutex_init(&clk->clk_mutex);
83 83
84 clk->clk_namemap = (struct namemap_cfg *) 84 clk->clk_namemap = (struct namemap_cfg *)
85 kzalloc(sizeof(struct namemap_cfg) * NUM_NAMEMAPS, GFP_KERNEL); 85 kzalloc(sizeof(struct namemap_cfg) * NUM_NAMEMAPS, GFP_KERNEL);
@@ -169,7 +169,7 @@ static u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) {
169 if (!c || !c->cntr.reg_ctrl_addr || !c->cntr.reg_cntr_addr) 169 if (!c || !c->cntr.reg_ctrl_addr || !c->cntr.reg_cntr_addr)
170 return 0; 170 return 0;
171 171
172 mutex_lock(&clk->clk_mutex); 172 nvgpu_mutex_acquire(&clk->clk_mutex);
173 173
174 /* Save the register */ 174 /* Save the register */
175 save_reg = gk20a_readl(g, c->cntr.reg_ctrl_addr); 175 save_reg = gk20a_readl(g, c->cntr.reg_ctrl_addr);
@@ -216,7 +216,7 @@ read_err:
216 gk20a_readl(g, c->cntr.reg_ctrl_addr); 216 gk20a_readl(g, c->cntr.reg_ctrl_addr);
217 gk20a_writel(g, c->cntr.reg_ctrl_addr, save_reg); 217 gk20a_writel(g, c->cntr.reg_ctrl_addr, save_reg);
218 gk20a_readl(g, c->cntr.reg_ctrl_addr); 218 gk20a_readl(g, c->cntr.reg_ctrl_addr);
219 mutex_unlock(&clk->clk_mutex); 219 nvgpu_mutex_release(&clk->clk_mutex);
220 220
221 return cntr; 221 return cntr;
222 222