diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/clk_gp106.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/clk_gp106.c | 273 |
1 files changed, 273 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.c b/drivers/gpu/nvgpu/gp106/clk_gp106.c new file mode 100644 index 00000000..4c9bc782 --- /dev/null +++ b/drivers/gpu/nvgpu/gp106/clk_gp106.c | |||
@@ -0,0 +1,273 @@ | |||
1 | /* | ||
2 | * GP106 Clocks | ||
3 | * | ||
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
17 | */ | ||
18 | |||
19 | #include <linux/clk.h> | ||
20 | #include <linux/delay.h> /* for mdelay */ | ||
21 | #include <linux/module.h> | ||
22 | #include <linux/debugfs.h> | ||
23 | #include <linux/uaccess.h> | ||
24 | #include <linux/clk/tegra.h> | ||
25 | #include <linux/tegra-fuse.h> | ||
26 | |||
27 | #include "gk20a/gk20a.h" | ||
28 | #include "hw_trim_gp106.h" | ||
29 | #include "clk_gp106.h" | ||
30 | #include "clk/clk_arb.h" | ||
31 | |||
32 | #define gk20a_dbg_clk(fmt, arg...) \ | ||
33 | gk20a_dbg(gpu_dbg_clk, fmt, ##arg) | ||
34 | |||
35 | #ifdef CONFIG_DEBUG_FS | ||
36 | static int clk_gp106_debugfs_init(struct gk20a *g); | ||
37 | #endif | ||
38 | |||
39 | #define NUM_NAMEMAPS 4 | ||
40 | #define XTAL4X_KHZ 108000 | ||
41 | |||
42 | |||
43 | static u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *); | ||
44 | static u16 gp106_clk_get_rate(struct gk20a *g, u32 api_domain); | ||
45 | static u32 gp106_crystal_clk_hz(struct gk20a *g) | ||
46 | { | ||
47 | return (XTAL4X_KHZ * 1000); | ||
48 | } | ||
49 | |||
50 | static u16 gp106_clk_get_rate(struct gk20a *g, u32 api_domain) | ||
51 | { | ||
52 | struct clk_gk20a *clk = &g->clk; | ||
53 | u32 freq_khz; | ||
54 | u32 i; | ||
55 | struct namemap_cfg *c = NULL; | ||
56 | |||
57 | for (i = 0; i < clk->namemap_num; i++) { | ||
58 | if (api_domain == clk->namemap_xlat_table[i]) { | ||
59 | c = &clk->clk_namemap[i]; | ||
60 | break; | ||
61 | } | ||
62 | } | ||
63 | |||
64 | if (!c) | ||
65 | return 0; | ||
66 | |||
67 | freq_khz = c->is_counter ? c->scale * gp106_get_rate_cntr(g, c) : | ||
68 | 0; /* TODO: PLL read */ | ||
69 | |||
70 | /* Convert to MHZ */ | ||
71 | return (u16) (freq_khz/1000); | ||
72 | } | ||
73 | |||
74 | static int gp106_init_clk_support(struct gk20a *g) { | ||
75 | struct clk_gk20a *clk = &g->clk; | ||
76 | u32 err = 0; | ||
77 | |||
78 | gk20a_dbg_fn(""); | ||
79 | |||
80 | mutex_init(&clk->clk_mutex); | ||
81 | |||
82 | clk->clk_namemap = (struct namemap_cfg *) | ||
83 | kzalloc(sizeof(struct namemap_cfg) * NUM_NAMEMAPS, GFP_KERNEL); | ||
84 | |||
85 | if (!clk->clk_namemap) | ||
86 | return -ENOMEM; | ||
87 | |||
88 | clk->namemap_xlat_table = kcalloc(NUM_NAMEMAPS, sizeof(u32), | ||
89 | GFP_KERNEL); | ||
90 | |||
91 | if (!clk->namemap_xlat_table) { | ||
92 | kfree(clk->clk_namemap); | ||
93 | return -ENOMEM; | ||
94 | } | ||
95 | |||
96 | clk->clk_namemap[0] = (struct namemap_cfg) { | ||
97 | .namemap = CLK_NAMEMAP_INDEX_GPC2CLK, | ||
98 | .is_enable = 1, | ||
99 | .is_counter = 1, | ||
100 | .g = g, | ||
101 | .cntr.reg_ctrl_addr = trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_r(), | ||
102 | .cntr.reg_ctrl_idx = | ||
103 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_source_gpc2clk_f(), | ||
104 | .cntr.reg_cntr_addr = trim_gpc_bcast_clk_cntr_ncgpcclk_cnt_r(), | ||
105 | .name = "gpc2clk", | ||
106 | .scale = 1 | ||
107 | }; | ||
108 | clk->namemap_xlat_table[0] = CTRL_CLK_DOMAIN_GPC2CLK; | ||
109 | clk->clk_namemap[1] = (struct namemap_cfg) { | ||
110 | .namemap = CLK_NAMEMAP_INDEX_SYS2CLK, | ||
111 | .is_enable = 1, | ||
112 | .is_counter = 1, | ||
113 | .g = g, | ||
114 | .cntr.reg_ctrl_addr = trim_sys_clk_cntr_ncsyspll_cfg_r(), | ||
115 | .cntr.reg_ctrl_idx = trim_sys_clk_cntr_ncsyspll_cfg_source_sys2clk_f(), | ||
116 | .cntr.reg_cntr_addr = trim_sys_clk_cntr_ncsyspll_cnt_r(), | ||
117 | .name = "sys2clk", | ||
118 | .scale = 1 | ||
119 | }; | ||
120 | clk->namemap_xlat_table[1] = CTRL_CLK_DOMAIN_SYS2CLK; | ||
121 | clk->clk_namemap[2] = (struct namemap_cfg) { | ||
122 | .namemap = CLK_NAMEMAP_INDEX_XBAR2CLK, | ||
123 | .is_enable = 1, | ||
124 | .is_counter = 1, | ||
125 | .g = g, | ||
126 | .cntr.reg_ctrl_addr = trim_sys_clk_cntr_ncltcpll_cfg_r(), | ||
127 | .cntr.reg_ctrl_idx = trim_sys_clk_cntr_ncltcpll_cfg_source_xbar2clk_f(), | ||
128 | .cntr.reg_cntr_addr = trim_sys_clk_cntr_ncltcpll_cnt_r(), | ||
129 | .name = "xbar2clk", | ||
130 | .scale = 1 | ||
131 | }; | ||
132 | clk->namemap_xlat_table[2] = CTRL_CLK_DOMAIN_XBAR2CLK; | ||
133 | clk->clk_namemap[3] = (struct namemap_cfg) { | ||
134 | .namemap = CLK_NAMEMAP_INDEX_DRAMCLK, | ||
135 | .is_enable = 1, | ||
136 | .is_counter = 1, | ||
137 | .g = g, | ||
138 | .cntr.reg_ctrl_addr = trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_r(), | ||
139 | .cntr.reg_ctrl_idx = | ||
140 | trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_source_dramdiv4_rec_clk1_f(), | ||
141 | .cntr.reg_cntr_addr = trim_fbpa_bcast_clk_cntr_ncltcclk_cnt_r(), | ||
142 | .name = "dramdiv2_rec_clk1", | ||
143 | .scale = 2 | ||
144 | }; | ||
145 | clk->namemap_xlat_table[3] = CTRL_CLK_DOMAIN_MCLK; | ||
146 | |||
147 | clk->namemap_num = NUM_NAMEMAPS; | ||
148 | |||
149 | clk->g = g; | ||
150 | |||
151 | #ifdef CONFIG_DEBUG_FS | ||
152 | if (!clk->debugfs_set) { | ||
153 | if (!clk_gp106_debugfs_init(g)) | ||
154 | clk->debugfs_set = true; | ||
155 | } | ||
156 | #endif | ||
157 | return err; | ||
158 | } | ||
159 | |||
160 | static u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) { | ||
161 | u32 save_reg; | ||
162 | u32 retries; | ||
163 | u32 cntr = 0; | ||
164 | |||
165 | struct clk_gk20a *clk = &g->clk; | ||
166 | |||
167 | if (!c || !c->cntr.reg_ctrl_addr || !c->cntr.reg_cntr_addr) | ||
168 | return 0; | ||
169 | |||
170 | mutex_lock(&clk->clk_mutex); | ||
171 | |||
172 | /* Save the register */ | ||
173 | save_reg = gk20a_readl(g, c->cntr.reg_ctrl_addr); | ||
174 | |||
175 | /* Disable and reset the current clock */ | ||
176 | gk20a_writel(g, c->cntr.reg_ctrl_addr, | ||
177 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_asserted_f() | | ||
178 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f()); | ||
179 | |||
180 | /* Force wb() */ | ||
181 | gk20a_readl(g, c->cntr.reg_ctrl_addr); | ||
182 | |||
183 | /* Wait for reset to happen */ | ||
184 | retries = CLK_DEFAULT_CNTRL_SETTLE_RETRIES; | ||
185 | do { | ||
186 | udelay(CLK_DEFAULT_CNTRL_SETTLE_USECS); | ||
187 | } while ((--retries) && (cntr = gk20a_readl(g, c->cntr.reg_cntr_addr))); | ||
188 | |||
189 | if (!retries) { | ||
190 | gk20a_err(dev_from_gk20a(g), | ||
191 | "unable to settle counter reset, bailing"); | ||
192 | goto read_err; | ||
193 | } | ||
194 | /* Program counter */ | ||
195 | gk20a_writel(g, c->cntr.reg_ctrl_addr, | ||
196 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_deasserted_f() | | ||
197 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_asserted_f() | | ||
198 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() | | ||
199 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() | | ||
200 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() | | ||
201 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_f(XTAL_CNTR_CLKS) | | ||
202 | c->cntr.reg_ctrl_idx); | ||
203 | gk20a_readl(g, c->cntr.reg_ctrl_addr); | ||
204 | |||
205 | udelay(XTAL_CNTR_DELAY); | ||
206 | |||
207 | cntr = XTAL_SCALE_TO_KHZ * gk20a_readl(g, c->cntr.reg_cntr_addr); | ||
208 | |||
209 | read_err: | ||
210 | /* reset and restore control register */ | ||
211 | gk20a_writel(g, c->cntr.reg_ctrl_addr, | ||
212 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_asserted_f() | | ||
213 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f()); | ||
214 | gk20a_readl(g, c->cntr.reg_ctrl_addr); | ||
215 | gk20a_writel(g, c->cntr.reg_ctrl_addr, save_reg); | ||
216 | gk20a_readl(g, c->cntr.reg_ctrl_addr); | ||
217 | mutex_unlock(&clk->clk_mutex); | ||
218 | |||
219 | return cntr; | ||
220 | |||
221 | } | ||
222 | |||
223 | #ifdef CONFIG_DEBUG_FS | ||
224 | static int gp106_get_rate_show(void *data , u64 *val) { | ||
225 | struct namemap_cfg *c = (struct namemap_cfg *) data; | ||
226 | struct gk20a *g = c->g; | ||
227 | |||
228 | *val = c->is_counter ? gp106_get_rate_cntr(g, c) : 0 /* TODO PLL read */; | ||
229 | return 0; | ||
230 | } | ||
231 | DEFINE_SIMPLE_ATTRIBUTE(get_rate_fops, gp106_get_rate_show, NULL, "%llu\n"); | ||
232 | |||
233 | |||
234 | static int clk_gp106_debugfs_init(struct gk20a *g) { | ||
235 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
236 | |||
237 | struct dentry *gpu_root = platform->debugfs; | ||
238 | struct dentry *clocks_root; | ||
239 | struct dentry *d; | ||
240 | unsigned int i; | ||
241 | |||
242 | if (NULL == (clocks_root = debugfs_create_dir("clocks", gpu_root))) | ||
243 | return -ENOMEM; | ||
244 | |||
245 | gk20a_dbg(gpu_dbg_info, "g=%p", g); | ||
246 | |||
247 | for (i = 0; i < g->clk.namemap_num; i++) { | ||
248 | if (g->clk.clk_namemap[i].is_enable) { | ||
249 | d = debugfs_create_file( | ||
250 | g->clk.clk_namemap[i].name, | ||
251 | S_IRUGO, | ||
252 | clocks_root, | ||
253 | &g->clk.clk_namemap[i], | ||
254 | &get_rate_fops); | ||
255 | if (!d) | ||
256 | goto err_out; | ||
257 | } | ||
258 | } | ||
259 | return 0; | ||
260 | |||
261 | err_out: | ||
262 | pr_err("%s: Failed to make debugfs node\n", __func__); | ||
263 | debugfs_remove_recursive(clocks_root); | ||
264 | return -ENOMEM; | ||
265 | } | ||
266 | #endif /* CONFIG_DEBUG_FS */ | ||
267 | |||
268 | void gp106_init_clk_ops(struct gpu_ops *gops) { | ||
269 | gops->clk.init_clk_support = gp106_init_clk_support; | ||
270 | gops->clk.get_crystal_clk_hz = gp106_crystal_clk_hz; | ||
271 | gops->clk.get_rate = gp106_clk_get_rate; | ||
272 | } | ||
273 | |||