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path: root/drivers/gpu/nvgpu/gp106/clk_gp106.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gp106/clk_gp106.c')
-rw-r--r--drivers/gpu/nvgpu/gp106/clk_gp106.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.c b/drivers/gpu/nvgpu/gp106/clk_gp106.c
index 13a401f0..e892ceda 100644
--- a/drivers/gpu/nvgpu/gp106/clk_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/clk_gp106.c
@@ -188,7 +188,7 @@ u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c)
188 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f()); 188 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f());
189 189
190 /* Force wb() */ 190 /* Force wb() */
191 gk20a_readl(g, c->cntr.reg_ctrl_addr); 191 (void) gk20a_readl(g, c->cntr.reg_ctrl_addr);
192 192
193 /* Wait for reset to happen */ 193 /* Wait for reset to happen */
194 retries = CLK_DEFAULT_CNTRL_SETTLE_RETRIES; 194 retries = CLK_DEFAULT_CNTRL_SETTLE_RETRIES;
@@ -209,7 +209,7 @@ u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c)
209 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() | 209 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() |
210 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_f(XTAL_CNTR_CLKS) | 210 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_f(XTAL_CNTR_CLKS) |
211 c->cntr.reg_ctrl_idx); 211 c->cntr.reg_ctrl_idx);
212 gk20a_readl(g, c->cntr.reg_ctrl_addr); 212 (void) gk20a_readl(g, c->cntr.reg_ctrl_addr);
213 213
214 nvgpu_udelay(XTAL_CNTR_DELAY); 214 nvgpu_udelay(XTAL_CNTR_DELAY);
215 215
@@ -220,9 +220,9 @@ read_err:
220 gk20a_writel(g, c->cntr.reg_ctrl_addr, 220 gk20a_writel(g, c->cntr.reg_ctrl_addr,
221 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_asserted_f() | 221 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_asserted_f() |
222 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f()); 222 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f());
223 gk20a_readl(g, c->cntr.reg_ctrl_addr); 223 (void) gk20a_readl(g, c->cntr.reg_ctrl_addr);
224 gk20a_writel(g, c->cntr.reg_ctrl_addr, save_reg); 224 gk20a_writel(g, c->cntr.reg_ctrl_addr, save_reg);
225 gk20a_readl(g, c->cntr.reg_ctrl_addr); 225 (void) gk20a_readl(g, c->cntr.reg_ctrl_addr);
226 nvgpu_mutex_release(&clk->clk_mutex); 226 nvgpu_mutex_release(&clk->clk_mutex);
227 227
228 return cntr; 228 return cntr;