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Diffstat (limited to 'drivers/gpu/nvgpu/gp106/bios_gp106.c')
-rw-r--r--drivers/gpu/nvgpu/gp106/bios_gp106.c123
1 files changed, 0 insertions, 123 deletions
diff --git a/drivers/gpu/nvgpu/gp106/bios_gp106.c b/drivers/gpu/nvgpu/gp106/bios_gp106.c
deleted file mode 100644
index d3e565ca..00000000
--- a/drivers/gpu/nvgpu/gp106/bios_gp106.c
+++ /dev/null
@@ -1,123 +0,0 @@
1/*
2 * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#include "gk20a/gk20a.h"
15#include "gm206/bios_gm206.h"
16
17#include "bios_gp106.h"
18
19#include <nvgpu/hw/gp106/hw_gc6_gp106.h>
20
21static void gp106_init_xmemsel_zm_nv_reg_array(struct gk20a *g, bool *condition,
22 u32 reg, u32 stride, u32 count, u32 data_table_offset)
23{
24 u8 i;
25 u32 data, strap, index;
26
27 if (*condition) {
28
29 strap = gk20a_readl(g, gc6_sci_strap_r()) & 0xf;
30
31 index = g->bios.mem_strap_xlat_tbl_ptr ?
32 gm206_bios_read_u8(g, g->bios.mem_strap_xlat_tbl_ptr +
33 strap) : strap;
34
35 for (i = 0; i < count; i++) {
36 data = gm206_bios_read_u32(g, data_table_offset + ((i *
37 g->bios.mem_strap_data_count + index) *
38 sizeof(u32)));
39 gk20a_writel(g, reg, data);
40 reg += stride;
41 }
42 }
43}
44
45static void gp106_init_condition(struct gk20a *g, bool *condition,
46 u32 condition_id)
47{
48 struct condition_entry entry;
49
50 entry.cond_addr = gm206_bios_read_u32(g, g->bios.condition_table_ptr +
51 sizeof(entry)*condition_id);
52 entry.cond_mask = gm206_bios_read_u32(g, g->bios.condition_table_ptr +
53 sizeof(entry)*condition_id + 4);
54 entry.cond_compare = gm206_bios_read_u32(g, g->bios.condition_table_ptr +
55 sizeof(entry)*condition_id + 8);
56
57 if ((gk20a_readl(g, entry.cond_addr) & entry.cond_mask)
58 != entry.cond_compare) {
59 *condition = false;
60 }
61}
62
63static int gp106_execute_script(struct gk20a *g, u32 offset)
64{
65 u8 opcode;
66 u32 ip;
67 u32 operand[8];
68 bool condition, end;
69 int status = 0;
70
71 ip = offset;
72 condition = true;
73 end = false;
74
75 while (!end) {
76
77 opcode = gm206_bios_read_u8(g, ip++);
78
79 switch (opcode) {
80
81 case INIT_XMEMSEL_ZM_NV_REG_ARRAY:
82 operand[0] = gm206_bios_read_u32(g, ip);
83 operand[1] = gm206_bios_read_u8(g, ip+4);
84 operand[2] = gm206_bios_read_u8(g, ip+5);
85 ip += 6;
86
87 gp106_init_xmemsel_zm_nv_reg_array(g, &condition,
88 operand[0], operand[1], operand[2], ip);
89 ip += operand[2] * sizeof(u32) *
90 g->bios.mem_strap_data_count;
91 break;
92
93 case INIT_CONDITION:
94 operand[0] = gm206_bios_read_u8(g, ip);
95 ip++;
96
97 gp106_init_condition(g, &condition, operand[0]);
98 break;
99
100 case INIT_RESUME:
101 condition = true;
102 break;
103
104 case INIT_DONE:
105 end = true;
106 break;
107
108 default:
109 gk20a_err(dev_from_gk20a(g), "opcode: 0x%02x", opcode);
110 end = true;
111 status = -EINVAL;
112 break;
113 }
114 }
115
116 return status;
117}
118
119void gp106_init_bios(struct gpu_ops *gops)
120{
121 gm206_init_bios(gops);
122 gops->bios.execute_script = gp106_execute_script;
123}