1 files changed, 66 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.h b/drivers/gpu/nvgpu/gp106/acr_gp106.h
new file mode 100644
index 00000000..79015a0a
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/acr_gp106.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __ACR_GP106_H_
+#define __ACR_GP106_H_
+
+#define GP106_FECS_UCODE_SIG "gp106/fecs_sig.bin"
+#define GP106_GPCCS_UCODE_SIG "gp106/gpccs_sig.bin"
+#define GP104_FECS_UCODE_SIG "gp104/fecs_sig.bin"
+#define GP104_GPCCS_UCODE_SIG "gp104/gpccs_sig.bin"
+
+
+int gp106_bootstrap_hs_flcn(struct gk20a *g);
+int gp106_prepare_ucode_blob(struct gk20a *g);
+int gp106_alloc_blob_space(struct gk20a *g,
+                size_t size, struct nvgpu_mem *mem);
+
+void gp106_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf);
+
+void lsfm_free_ucode_img_res(struct gk20a *g,
+                                    struct flcn_ucode_img_v1 *p_img);
+void lsfm_free_nonpmu_ucode_img_res(struct gk20a *g,
+                                           struct flcn_ucode_img_v1 *p_img);
+int lsf_gen_wpr_requirements(struct gk20a *g,
+                struct ls_flcn_mgr_v1 *plsfm);
+void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm);
+void lsfm_fill_static_lsb_hdr_info(struct gk20a *g,
+        u32 falcon_id, struct lsfm_managed_ucode_img_v2 *pnode);
+int gp106_pmu_populate_loader_cfg(struct gk20a *g,
+        void *lsfm, u32 *p_bl_gen_desc_size);
+
+int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img);
+int fecs_ucode_details(struct gk20a *g,
+                struct flcn_ucode_img_v1 *p_img);
+int gpccs_ucode_details(struct gk20a *g,
+                struct flcn_ucode_img_v1 *p_img);
+int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm,
+        struct flcn_ucode_img_v1 *ucode_image, u32 falcon_id);
+int lsfm_discover_ucode_images(struct gk20a *g,
+        struct ls_flcn_mgr_v1 *plsfm);
+void lsfm_init_wpr_contents(struct gk20a *g,
+                struct ls_flcn_mgr_v1 *plsfm, struct nvgpu_mem *nonwpr);
+int gp106_flcn_populate_bl_dmem_desc(struct gk20a *g,
+        void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid);
+int lsfm_fill_flcn_bl_gen_desc(struct gk20a *g,
+                struct lsfm_managed_ucode_img_v2 *pnode);
+#endif /*__PMU_GP106_H_*/