diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/acr_gp106.h')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/acr_gp106.h | 128 |
1 files changed, 128 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.h b/drivers/gpu/nvgpu/gp106/acr_gp106.h new file mode 100644 index 00000000..cd555eb8 --- /dev/null +++ b/drivers/gpu/nvgpu/gp106/acr_gp106.h | |||
@@ -0,0 +1,128 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ACR_GP106_H_ | ||
15 | #define __ACR_GP106_H_ | ||
16 | |||
17 | #include "gm20b/acr_gm20b.h" | ||
18 | #include "gm206/acr_gm206.h" | ||
19 | |||
20 | #define GP106_FECS_UCODE_SIG "gp106/fecs_sig.bin" | ||
21 | #define GP106_GPCCS_UCODE_SIG "gp106/gpccs_sig.bin" | ||
22 | #define GP104_FECS_UCODE_SIG "gp104/fecs_sig.bin" | ||
23 | #define GP104_GPCCS_UCODE_SIG "gp104/gpccs_sig.bin" | ||
24 | |||
25 | struct lsf_ucode_desc_v1 { | ||
26 | u8 prd_keys[2][16]; | ||
27 | u8 dbg_keys[2][16]; | ||
28 | u32 b_prd_present; | ||
29 | u32 b_dbg_present; | ||
30 | u32 falcon_id; | ||
31 | u32 bsupports_versioning; | ||
32 | u32 version; | ||
33 | u32 dep_map_count; | ||
34 | u8 dep_map[LSF_FALCON_ID_END * 2 * 4]; | ||
35 | u8 kdf[16]; | ||
36 | }; | ||
37 | |||
38 | struct lsf_wpr_header_v1 { | ||
39 | u32 falcon_id; | ||
40 | u32 lsb_offset; | ||
41 | u32 bootstrap_owner; | ||
42 | u32 lazy_bootstrap; | ||
43 | u32 bin_version; | ||
44 | u32 status; | ||
45 | }; | ||
46 | |||
47 | struct lsf_lsb_header_v1 { | ||
48 | struct lsf_ucode_desc_v1 signature; | ||
49 | u32 ucode_off; | ||
50 | u32 ucode_size; | ||
51 | u32 data_size; | ||
52 | u32 bl_code_size; | ||
53 | u32 bl_imem_off; | ||
54 | u32 bl_data_off; | ||
55 | u32 bl_data_size; | ||
56 | u32 app_code_off; | ||
57 | u32 app_code_size; | ||
58 | u32 app_data_off; | ||
59 | u32 app_data_size; | ||
60 | u32 flags; | ||
61 | }; | ||
62 | |||
63 | struct flcn_ucode_img_v1 { | ||
64 | u32 *header; /*only some falcons have header*/ | ||
65 | u32 *data; | ||
66 | struct pmu_ucode_desc_v1 *desc; /*only some falcons have descriptor*/ | ||
67 | u32 data_size; | ||
68 | void *fw_ver; /*NV2080_CTRL_GPU_GET_FIRMWARE_VERSION_PARAMS struct*/ | ||
69 | u8 load_entire_os_data; /* load the whole osData section at boot time.*/ | ||
70 | struct lsf_ucode_desc_v1 *lsf_desc; /* NULL if not a light secure falcon.*/ | ||
71 | u8 free_res_allocs;/*True if there a resources to freed by the client.*/ | ||
72 | u32 flcn_inst; | ||
73 | }; | ||
74 | |||
75 | struct lsfm_managed_ucode_img_v2 { | ||
76 | struct lsfm_managed_ucode_img_v2 *next; | ||
77 | struct lsf_wpr_header_v1 wpr_header; | ||
78 | struct lsf_lsb_header_v1 lsb_header; | ||
79 | union flcn_bl_generic_desc_v1 bl_gen_desc; | ||
80 | u32 bl_gen_desc_size; | ||
81 | u32 full_ucode_size; | ||
82 | struct flcn_ucode_img_v1 ucode_img; | ||
83 | }; | ||
84 | struct ls_flcn_mgr_v1 { | ||
85 | u16 managed_flcn_cnt; | ||
86 | u32 wpr_size; | ||
87 | u32 disable_mask; | ||
88 | struct lsfm_managed_ucode_img_v2 *ucode_img_list; | ||
89 | void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/ | ||
90 | }; | ||
91 | |||
92 | struct flcn_acr_region_prop_v1 { | ||
93 | u32 start_addr; | ||
94 | u32 end_addr; | ||
95 | u32 region_id; | ||
96 | u32 read_mask; | ||
97 | u32 write_mask; | ||
98 | u32 client_mask; | ||
99 | u32 shadowmMem_startaddress; | ||
100 | }; | ||
101 | |||
102 | /*! | ||
103 | * no_regions - Number of regions used. | ||
104 | * region_props - Region properties | ||
105 | */ | ||
106 | struct flcn_acr_regions_v1 { | ||
107 | u32 no_regions; | ||
108 | struct flcn_acr_region_prop_v1 region_props[T210_FLCN_ACR_MAX_REGIONS]; | ||
109 | }; | ||
110 | |||
111 | struct flcn_acr_desc_v1 { | ||
112 | union { | ||
113 | u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; | ||
114 | } ucode_reserved_space; | ||
115 | u32 signatures[4]; | ||
116 | /*Always 1st*/ | ||
117 | u32 wpr_region_id; | ||
118 | u32 wpr_offset; | ||
119 | u32 mmu_mem_range; | ||
120 | struct flcn_acr_regions_v1 regions; | ||
121 | u32 nonwpr_ucode_blob_size; | ||
122 | u64 nonwpr_ucode_blob_start; | ||
123 | u32 dummy[4]; //ACR_BSI_VPR_DESC | ||
124 | }; | ||
125 | |||
126 | void gp106_init_secure_pmu(struct gpu_ops *gops); | ||
127 | |||
128 | #endif /*__PMU_GP106_H_*/ | ||