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Diffstat (limited to 'drivers/gpu/nvgpu/gp106/acr_gp106.c')
-rw-r--r--drivers/gpu/nvgpu/gp106/acr_gp106.c24
1 files changed, 8 insertions, 16 deletions
diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c
index 0dfa8e0e..31ddecf0 100644
--- a/drivers/gpu/nvgpu/gp106/acr_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -35,17 +35,13 @@
35#include "gm20b/acr_gm20b.h" 35#include "gm20b/acr_gm20b.h"
36#include "gp106/acr_gp106.h" 36#include "gp106/acr_gp106.h"
37#include "gp106/pmu_gp106.h" 37#include "gp106/pmu_gp106.h"
38#include "gv100/acr_gv100.h"
38 39
39#include "sec2_gp106.h" 40#include "sec2_gp106.h"
40 41
41#include <nvgpu/hw/gp106/hw_psec_gp106.h> 42#include <nvgpu/hw/gp106/hw_psec_gp106.h>
42#include <nvgpu/hw/gp106/hw_pwr_gp106.h> 43#include <nvgpu/hw/gp106/hw_pwr_gp106.h>
43 44
44#ifdef CONFIG_TEGRA_19x_GPU
45#include "nvgpu_gpuid_t19x.h"
46#include "acr_t19x.h"
47#endif
48
49/*Defines*/ 45/*Defines*/
50#define gp106_dbg_pmu(fmt, arg...) \ 46#define gp106_dbg_pmu(fmt, arg...) \
51 gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) 47 gk20a_dbg(gpu_dbg_pmu, fmt, ##arg)
@@ -200,17 +196,15 @@ int fecs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img)
200 GP106_FECS_UCODE_SIG, 196 GP106_FECS_UCODE_SIG,
201 NVGPU_REQUEST_FIRMWARE_NO_SOC); 197 NVGPU_REQUEST_FIRMWARE_NO_SOC);
202 break; 198 break;
203#if defined(CONFIG_TEGRA_19x_GPU) 199 case NVGPU_GPUID_GV11B:
204 case TEGRA_19x_GPUID:
205 fecs_sig = nvgpu_request_firmware(g, 200 fecs_sig = nvgpu_request_firmware(g,
206 GM20B_FECS_UCODE_SIG, 0); 201 GM20B_FECS_UCODE_SIG, 0);
207 break; 202 break;
208 case BIGGPU_19x_GPUID: 203 case NVGPU_GPUID_GV100:
209 fecs_sig = nvgpu_request_firmware(g, 204 fecs_sig = nvgpu_request_firmware(g,
210 BIGGPU_FECS_UCODE_SIG, 205 GV100_FECS_UCODE_SIG,
211 NVGPU_REQUEST_FIRMWARE_NO_SOC); 206 NVGPU_REQUEST_FIRMWARE_NO_SOC);
212 break; 207 break;
213#endif
214 default: 208 default:
215 nvgpu_err(g, "no support for GPUID %x", ver); 209 nvgpu_err(g, "no support for GPUID %x", ver);
216 } 210 }
@@ -297,17 +291,15 @@ int gpccs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img)
297 GP106_GPCCS_UCODE_SIG, 291 GP106_GPCCS_UCODE_SIG,
298 NVGPU_REQUEST_FIRMWARE_NO_SOC); 292 NVGPU_REQUEST_FIRMWARE_NO_SOC);
299 break; 293 break;
300#if defined(CONFIG_TEGRA_19x_GPU) 294 case NVGPU_GPUID_GV11B:
301 case TEGRA_19x_GPUID:
302 gpccs_sig = nvgpu_request_firmware(g, 295 gpccs_sig = nvgpu_request_firmware(g,
303 T18x_GPCCS_UCODE_SIG, 0); 296 T18x_GPCCS_UCODE_SIG, 0);
304 break; 297 break;
305 case BIGGPU_19x_GPUID: 298 case NVGPU_GPUID_GV100:
306 gpccs_sig = nvgpu_request_firmware(g, 299 gpccs_sig = nvgpu_request_firmware(g,
307 BIGGPU_GPCCS_UCODE_SIG, 300 GV100_GPCCS_UCODE_SIG,
308 NVGPU_REQUEST_FIRMWARE_NO_SOC); 301 NVGPU_REQUEST_FIRMWARE_NO_SOC);
309 break; 302 break;
310#endif
311 default: 303 default:
312 nvgpu_err(g, "no support for GPUID %x", ver); 304 nvgpu_err(g, "no support for GPUID %x", ver);
313 } 305 }