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Diffstat (limited to 'drivers/gpu/nvgpu/gp106/acr_gp106.c')
-rw-r--r--drivers/gpu/nvgpu/gp106/acr_gp106.c7
1 files changed, 2 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c
index 2ea2f817..0b4b86f4 100644
--- a/drivers/gpu/nvgpu/gp106/acr_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c
@@ -37,8 +37,8 @@ typedef int (*get_ucode_details)(struct gk20a *g,
37 37
38/* Both size and address of WPR need to be 128K-aligned */ 38/* Both size and address of WPR need to be 128K-aligned */
39#define WPR_ALIGNMENT 0x20000 39#define WPR_ALIGNMENT 0x20000
40#define GP106_DGPU_NONWPR 0x10000000 /* start from 256MB location at VIDMEM */ 40#define GP106_DGPU_NONWPR 0x18000000
41#define GP106_DGPU_WPR 0x20000000 41#define GP106_DGPU_WPR (GP106_DGPU_NONWPR + 0x400000)
42#define DGPU_WPR_SIZE 0x100000 42#define DGPU_WPR_SIZE 0x100000
43 43
44/*Externs*/ 44/*Externs*/
@@ -365,9 +365,6 @@ int gp106_prepare_ucode_blob(struct gk20a *g)
365 gm20b_mm_mmu_vpr_info_fetch(g); 365 gm20b_mm_mmu_vpr_info_fetch(g);
366 gr_gk20a_init_ctxsw_ucode(g); 366 gr_gk20a_init_ctxsw_ucode(g);
367 367
368 if (g->ops.fb.dump_vpr_wpr_info)
369 g->ops.fb.dump_vpr_wpr_info(g);
370
371 g->ops.pmu.get_wpr(g, &wpr_inf); 368 g->ops.pmu.get_wpr(g, &wpr_inf);
372 gp106_dbg_pmu("wpr carveout base:%llx\n", (wpr_inf.wpr_base)); 369 gp106_dbg_pmu("wpr carveout base:%llx\n", (wpr_inf.wpr_base));
373 gp106_dbg_pmu("wpr carveout size :%x\n", (u32)wpr_inf.size); 370 gp106_dbg_pmu("wpr carveout size :%x\n", (u32)wpr_inf.size);