diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/acr_gp106.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/acr_gp106.c | 132 |
1 files changed, 0 insertions, 132 deletions
diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c index 9b8558db..7bb099e5 100644 --- a/drivers/gpu/nvgpu/gp106/acr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c | |||
@@ -1191,135 +1191,3 @@ int lsf_gen_wpr_requirements(struct gk20a *g, | |||
1191 | plsfm->wpr_size = wpr_offset; | 1191 | plsfm->wpr_size = wpr_offset; |
1192 | return 0; | 1192 | return 0; |
1193 | } | 1193 | } |
1194 | |||
1195 | /*Loads ACR bin to FB mem and bootstraps PMU with bootloader code | ||
1196 | * start and end are addresses of ucode blob in non-WPR region*/ | ||
1197 | int gp106_bootstrap_hs_flcn(struct gk20a *g) | ||
1198 | { | ||
1199 | struct mm_gk20a *mm = &g->mm; | ||
1200 | struct vm_gk20a *vm = mm->pmu.vm; | ||
1201 | int err = 0; | ||
1202 | u64 *acr_dmem; | ||
1203 | u32 img_size_in_bytes = 0; | ||
1204 | u32 status; | ||
1205 | struct acr_desc *acr = &g->acr; | ||
1206 | struct nvgpu_firmware *acr_fw = acr->acr_fw; | ||
1207 | struct flcn_bl_dmem_desc_v1 *bl_dmem_desc = &acr->bl_dmem_desc_v1; | ||
1208 | u32 *acr_ucode_header_t210_load; | ||
1209 | u32 *acr_ucode_data_t210_load; | ||
1210 | struct wpr_carveout_info wpr_inf; | ||
1211 | |||
1212 | gp106_dbg_pmu(g, " "); | ||
1213 | |||
1214 | if (!acr_fw) { | ||
1215 | /*First time init case*/ | ||
1216 | acr_fw = nvgpu_request_firmware(g, | ||
1217 | GM20B_HSBIN_PMU_UCODE_IMAGE, | ||
1218 | NVGPU_REQUEST_FIRMWARE_NO_SOC); | ||
1219 | if (!acr_fw) { | ||
1220 | nvgpu_err(g, "pmu ucode get fail"); | ||
1221 | return -ENOENT; | ||
1222 | } | ||
1223 | acr->acr_fw = acr_fw; | ||
1224 | acr->hsbin_hdr = (struct bin_hdr *)acr_fw->data; | ||
1225 | acr->fw_hdr = (struct acr_fw_header *)(acr_fw->data + | ||
1226 | acr->hsbin_hdr->header_offset); | ||
1227 | acr_ucode_data_t210_load = (u32 *)(acr_fw->data + | ||
1228 | acr->hsbin_hdr->data_offset); | ||
1229 | acr_ucode_header_t210_load = (u32 *)(acr_fw->data + | ||
1230 | acr->fw_hdr->hdr_offset); | ||
1231 | img_size_in_bytes = ALIGN((acr->hsbin_hdr->data_size), 256); | ||
1232 | |||
1233 | /* Lets patch the signatures first.. */ | ||
1234 | if (acr_ucode_patch_sig(g, acr_ucode_data_t210_load, | ||
1235 | (u32 *)(acr_fw->data + | ||
1236 | acr->fw_hdr->sig_prod_offset), | ||
1237 | (u32 *)(acr_fw->data + | ||
1238 | acr->fw_hdr->sig_dbg_offset), | ||
1239 | (u32 *)(acr_fw->data + | ||
1240 | acr->fw_hdr->patch_loc), | ||
1241 | (u32 *)(acr_fw->data + | ||
1242 | acr->fw_hdr->patch_sig)) < 0) { | ||
1243 | nvgpu_err(g, "patch signatures fail"); | ||
1244 | err = -1; | ||
1245 | goto err_release_acr_fw; | ||
1246 | } | ||
1247 | err = nvgpu_dma_alloc_map_sys(vm, img_size_in_bytes, | ||
1248 | &acr->acr_ucode); | ||
1249 | if (err) { | ||
1250 | err = -ENOMEM; | ||
1251 | goto err_release_acr_fw; | ||
1252 | } | ||
1253 | |||
1254 | g->ops.pmu.get_wpr(g, &wpr_inf); | ||
1255 | |||
1256 | acr_dmem = (u64 *) | ||
1257 | &(((u8 *)acr_ucode_data_t210_load)[ | ||
1258 | acr_ucode_header_t210_load[2]]); | ||
1259 | acr->acr_dmem_desc_v1 = (struct flcn_acr_desc_v1 *)((u8 *)( | ||
1260 | acr->acr_ucode.cpu_va) + acr_ucode_header_t210_load[2]); | ||
1261 | ((struct flcn_acr_desc_v1 *)acr_dmem)->nonwpr_ucode_blob_start = | ||
1262 | wpr_inf.nonwpr_base; | ||
1263 | ((struct flcn_acr_desc_v1 *)acr_dmem)->nonwpr_ucode_blob_size = | ||
1264 | wpr_inf.size; | ||
1265 | ((struct flcn_acr_desc_v1 *)acr_dmem)->regions.no_regions = 1; | ||
1266 | ((struct flcn_acr_desc_v1 *)acr_dmem)->wpr_offset = 0; | ||
1267 | |||
1268 | ((struct flcn_acr_desc_v1 *)acr_dmem)->wpr_region_id = 1; | ||
1269 | ((struct flcn_acr_desc_v1 *)acr_dmem)->regions.region_props[ | ||
1270 | 0].region_id = 1; | ||
1271 | ((struct flcn_acr_desc_v1 *)acr_dmem)->regions.region_props[ | ||
1272 | 0].start_addr = (wpr_inf.wpr_base ) >> 8; | ||
1273 | ((struct flcn_acr_desc_v1 *)acr_dmem)->regions.region_props[ | ||
1274 | 0].end_addr = ((wpr_inf.wpr_base) + wpr_inf.size) >> 8; | ||
1275 | ((struct flcn_acr_desc_v1 *)acr_dmem)->regions.region_props[ | ||
1276 | 0].shadowmMem_startaddress = wpr_inf.nonwpr_base >> 8; | ||
1277 | |||
1278 | nvgpu_mem_wr_n(g, &acr->acr_ucode, 0, | ||
1279 | acr_ucode_data_t210_load, img_size_in_bytes); | ||
1280 | |||
1281 | /* | ||
1282 | * In order to execute this binary, we will be using | ||
1283 | * a bootloader which will load this image into PMU IMEM/DMEM. | ||
1284 | * Fill up the bootloader descriptor for PMU HAL to use.. | ||
1285 | * TODO: Use standard descriptor which the generic bootloader is | ||
1286 | * checked in. | ||
1287 | */ | ||
1288 | |||
1289 | bl_dmem_desc->signature[0] = 0; | ||
1290 | bl_dmem_desc->signature[1] = 0; | ||
1291 | bl_dmem_desc->signature[2] = 0; | ||
1292 | bl_dmem_desc->signature[3] = 0; | ||
1293 | bl_dmem_desc->ctx_dma = GK20A_PMU_DMAIDX_VIRT; | ||
1294 | flcn64_set_dma( &bl_dmem_desc->code_dma_base, | ||
1295 | acr->acr_ucode.gpu_va); | ||
1296 | bl_dmem_desc->non_sec_code_off = acr_ucode_header_t210_load[0]; | ||
1297 | bl_dmem_desc->non_sec_code_size = acr_ucode_header_t210_load[1]; | ||
1298 | bl_dmem_desc->sec_code_off = acr_ucode_header_t210_load[5]; | ||
1299 | bl_dmem_desc->sec_code_size = acr_ucode_header_t210_load[6]; | ||
1300 | bl_dmem_desc->code_entry_point = 0; /* Start at 0th offset */ | ||
1301 | flcn64_set_dma( &bl_dmem_desc->data_dma_base, | ||
1302 | acr->acr_ucode.gpu_va + | ||
1303 | (acr_ucode_header_t210_load[2])); | ||
1304 | bl_dmem_desc->data_size = acr_ucode_header_t210_load[3]; | ||
1305 | } else { | ||
1306 | acr->acr_dmem_desc->nonwpr_ucode_blob_size = 0; | ||
1307 | } | ||
1308 | |||
1309 | status = pmu_exec_gen_bl(g, bl_dmem_desc, 1); | ||
1310 | if (status != 0) { | ||
1311 | err = status; | ||
1312 | goto err_free_ucode_map; | ||
1313 | } | ||
1314 | |||
1315 | /* sec2 reset - to keep it idle */ | ||
1316 | nvgpu_flcn_reset(&g->sec2_flcn); | ||
1317 | |||
1318 | return 0; | ||
1319 | err_free_ucode_map: | ||
1320 | nvgpu_dma_unmap_free(vm, &acr->acr_ucode); | ||
1321 | err_release_acr_fw: | ||
1322 | nvgpu_release_firmware(g, acr_fw); | ||
1323 | acr->acr_fw = NULL; | ||
1324 | return err; | ||
1325 | } | ||