1 files changed, 126 insertions, 7 deletions

diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c
index 7bb099e5..b1150e29 100644
--- a/drivers/gpu/nvgpu/gp106/acr_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c
@@ -93,7 +93,7 @@ int gp106_alloc_blob_space(struct gk20a *g,
                 return 0;
         }
 
-        g->ops.pmu.get_wpr(g, &wpr_inf);
+        g->acr.get_wpr_info(g, &wpr_inf);
 
         /*
          * Even though this mem_desc wouldn't be used, the wpr region needs to
@@ -456,7 +456,7 @@ int gp106_prepare_ucode_blob(struct gk20a *g)
         memset((void *)plsfm, 0, sizeof(struct ls_flcn_mgr_v1));
         gr_gk20a_init_ctxsw_ucode(g);
 
-        g->ops.pmu.get_wpr(g, &wpr_inf);
+        g->acr.get_wpr_info(g, &wpr_inf);
         gp106_dbg_pmu(g, "wpr carveout base:%llx\n", (wpr_inf.wpr_base));
         gp106_dbg_pmu(g, "wpr carveout size :%x\n", (u32)wpr_inf.size);
 
@@ -479,7 +479,7 @@ int gp106_prepare_ucode_blob(struct gk20a *g)
                 }
 
                 /*Alloc memory to hold ucode blob contents*/
-                err = g->ops.pmu.alloc_blob_space(g, plsfm->wpr_size
+                err = g->acr.alloc_blob_space(g, plsfm->wpr_size
                                                         ,&g->acr.ucode_blob);
                 if (err) {
                         goto exit_err;
@@ -557,7 +557,7 @@ int lsfm_discover_ucode_images(struct gk20a *g,
 
         /*0th index is always PMU which is already handled in earlier
         if condition*/
-        for (i = 1; i < (MAX_SUPPORTED_LSFM); i++) {
+        for (i = 1; i < g->acr.max_supported_lsfm; i++) {
                 memset(&ucode_img, 0, sizeof(ucode_img));
                 if (pmu_acr_supp_ucode_list[i](g, &ucode_img) == 0) {
                         if (ucode_img.lsf_desc != NULL) {
@@ -626,7 +626,7 @@ int gp106_pmu_populate_loader_cfg(struct gk20a *g,
          * physical addresses of each respective segment.
          */
         addr_base = p_lsfm->lsb_header.ucode_off;
-        g->ops.pmu.get_wpr(g, &wpr_inf);
+        g->acr.get_wpr_info(g, &wpr_inf);
         addr_base += (wpr_inf.wpr_base);
 
         gp106_dbg_pmu(g, "pmu loader cfg addrbase 0x%llx\n", addr_base);
@@ -701,7 +701,7 @@ int gp106_flcn_populate_bl_dmem_desc(struct gk20a *g,
          * physical addresses of each respective segment.
          */
         addr_base = p_lsfm->lsb_header.ucode_off;
-        g->ops.pmu.get_wpr(g, &wpr_inf);
+        g->acr.get_wpr_info(g, &wpr_inf);
         addr_base += wpr_inf.wpr_base;
 
         gp106_dbg_pmu(g, "falcon ID %x", p_lsfm->wpr_header.falcon_id);
@@ -1017,7 +1017,7 @@ int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm,
 
         /* Fill in static WPR header info*/
         pnode->wpr_header.falcon_id = falcon_id;
-        pnode->wpr_header.bootstrap_owner = g->bootstrap_owner;
+        pnode->wpr_header.bootstrap_owner = g->acr.bootstrap_owner;
         pnode->wpr_header.status = LSF_IMAGE_STATUS_COPY;
 
         pnode->wpr_header.lazy_bootstrap =
@@ -1030,6 +1030,7 @@ int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm,
         pnode->wpr_header.bin_version = pnode->lsb_header.signature.version;
         pnode->next = plsfm->ucode_img_list;
         plsfm->ucode_img_list = pnode;
+
         return 0;
 }
 
@@ -1191,3 +1192,121 @@ int lsf_gen_wpr_requirements(struct gk20a *g,
         plsfm->wpr_size = wpr_offset;
         return 0;
 }
+
+int gp106_acr_patch_wpr_info_to_ucode(struct gk20a *g, struct nvgpu_acr *acr,
+                struct hs_acr *acr_desc, bool is_recovery)
+{
+        struct nvgpu_firmware *acr_fw = acr_desc->acr_fw;
+        struct acr_fw_header *acr_fw_hdr = NULL;
+        struct bin_hdr *acr_fw_bin_hdr = NULL;
+        struct flcn_acr_desc_v1 *acr_dmem_desc;
+        struct wpr_carveout_info wpr_inf;
+        u32 *acr_ucode_header = NULL;
+        u32 *acr_ucode_data = NULL;
+
+        nvgpu_log_fn(g, " ");
+
+        acr_fw_bin_hdr = (struct bin_hdr *)acr_fw->data;
+        acr_fw_hdr = (struct acr_fw_header *)
+                (acr_fw->data + acr_fw_bin_hdr->header_offset);
+
+        acr_ucode_data = (u32 *)(acr_fw->data + acr_fw_bin_hdr->data_offset);
+        acr_ucode_header = (u32 *)(acr_fw->data + acr_fw_hdr->hdr_offset);
+
+        acr->get_wpr_info(g, &wpr_inf);
+
+        acr_dmem_desc = (struct flcn_acr_desc_v1 *)
+                &(((u8 *)acr_ucode_data)[acr_ucode_header[2U]]);
+
+        acr_dmem_desc->nonwpr_ucode_blob_start = wpr_inf.nonwpr_base;
+        acr_dmem_desc->nonwpr_ucode_blob_size = wpr_inf.size;
+        acr_dmem_desc->regions.no_regions = 1U;
+        acr_dmem_desc->wpr_offset = 0U;
+
+        acr_dmem_desc->wpr_region_id = 1U;
+        acr_dmem_desc->regions.region_props[0U].region_id = 1U;
+        acr_dmem_desc->regions.region_props[0U].start_addr =
+                (wpr_inf.wpr_base) >> 8U;
+        acr_dmem_desc->regions.region_props[0U].end_addr =
+                ((wpr_inf.wpr_base) + wpr_inf.size) >> 8U;
+        acr_dmem_desc->regions.region_props[0U].shadowmMem_startaddress =
+                wpr_inf.nonwpr_base >> 8U;
+
+        return 0;
+}
+
+int gp106_acr_fill_bl_dmem_desc(struct gk20a *g,
+        struct nvgpu_acr *acr, struct hs_acr *acr_desc,
+        u32 *acr_ucode_header)
+{
+        struct nvgpu_mem *acr_ucode_mem = &acr_desc->acr_ucode;
+        struct flcn_bl_dmem_desc_v1 *bl_dmem_desc =
+                &acr_desc->bl_dmem_desc_v1;
+
+        nvgpu_log_fn(g, " ");
+
+        memset(bl_dmem_desc, 0U, sizeof(struct flcn_bl_dmem_desc_v1));
+
+        bl_dmem_desc->signature[0] = 0U;
+        bl_dmem_desc->signature[1] = 0U;
+        bl_dmem_desc->signature[2] = 0U;
+        bl_dmem_desc->signature[3] = 0U;
+        bl_dmem_desc->ctx_dma = GK20A_PMU_DMAIDX_VIRT;
+
+        flcn64_set_dma(&bl_dmem_desc->code_dma_base,
+                acr_ucode_mem->gpu_va);
+
+        bl_dmem_desc->non_sec_code_off  = acr_ucode_header[0U];
+        bl_dmem_desc->non_sec_code_size = acr_ucode_header[1U];
+        bl_dmem_desc->sec_code_off = acr_ucode_header[5U];
+        bl_dmem_desc->sec_code_size = acr_ucode_header[6U];
+        bl_dmem_desc->code_entry_point = 0U;
+
+        flcn64_set_dma(&bl_dmem_desc->data_dma_base,
+                acr_ucode_mem->gpu_va + acr_ucode_header[2U]);
+
+        bl_dmem_desc->data_size = acr_ucode_header[3U];
+
+        return 0;
+}
+
+static void nvgpu_gp106_acr_default_sw_init(struct gk20a *g, struct hs_acr *hs_acr)
+{
+        struct hs_flcn_bl *hs_bl = &hs_acr->acr_hs_bl;
+
+        nvgpu_log_fn(g, " ");
+
+        hs_bl->bl_fw_name = HSBIN_ACR_BL_UCODE_IMAGE;
+
+        hs_acr->acr_type = ACR_DEFAULT;
+        hs_acr->acr_fw_name = HSBIN_ACR_UCODE_IMAGE;
+
+        hs_acr->ptr_bl_dmem_desc = &hs_acr->bl_dmem_desc_v1;
+        hs_acr->bl_dmem_desc_size = sizeof(struct flcn_bl_dmem_desc_v1);
+
+        hs_acr->acr_flcn = &g->sec2_flcn;
+        hs_acr->acr_flcn_setup_hw_and_bl_bootstrap =
+                gp106_sec2_setup_hw_and_bl_bootstrap;
+}
+
+void nvgpu_gp106_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
+{
+        nvgpu_log_fn(g, " ");
+
+        acr->g = g;
+
+        acr->bootstrap_owner = LSF_FALCON_ID_SEC2;
+        acr->max_supported_lsfm = MAX_SUPPORTED_LSFM;
+
+        nvgpu_gp106_acr_default_sw_init(g, &acr->acr);
+
+        acr->get_wpr_info = gp106_wpr_info;
+        acr->alloc_blob_space = gp106_alloc_blob_space;
+        acr->bootstrap_hs_acr = gm20b_bootstrap_hs_acr;
+        acr->patch_wpr_info_to_ucode =
+                gp106_acr_patch_wpr_info_to_ucode;
+        acr->acr_fill_bl_dmem_desc =
+                gp106_acr_fill_bl_dmem_desc;
+
+        acr->remove_support = gm20b_remove_acr_support;
+}