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Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r--drivers/gpu/nvgpu/gm20b/gr_gm20b.c9
-rw-r--r--drivers/gpu/nvgpu/gm20b/hal_gm20b.c16
2 files changed, 0 insertions, 25 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index ef46c1ee..0d032be0 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -737,7 +737,6 @@ u32 gr_gm20b_get_tpc_num(struct gk20a *g, u32 addr)
737 return 0; 737 return 0;
738} 738}
739 739
740#ifdef CONFIG_TEGRA_ACR
741static void gr_gm20b_load_gpccs_with_bootloader(struct gk20a *g) 740static void gr_gm20b_load_gpccs_with_bootloader(struct gk20a *g)
742{ 741{
743 struct gk20a_ctxsw_ucode_info *ucode_info = &g->ctxsw_ucode_info; 742 struct gk20a_ctxsw_ucode_info *ucode_info = &g->ctxsw_ucode_info;
@@ -830,14 +829,6 @@ int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
830 829
831 return 0; 830 return 0;
832} 831}
833#else
834
835int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
836{
837 return -EPERM;
838}
839
840#endif
841 832
842void gr_gm20b_detect_sm_arch(struct gk20a *g) 833void gr_gm20b_detect_sm_arch(struct gk20a *g)
843{ 834{
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 227b6b6c..bb18d2d7 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -634,7 +634,6 @@ int gm20b_init_hal(struct gk20a *g)
634 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); 634 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
635 __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); 635 __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
636 636
637#ifdef CONFIG_TEGRA_ACR
638 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { 637 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
639 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); 638 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
640 } else { 639 } else {
@@ -646,21 +645,6 @@ int gm20b_init_hal(struct gk20a *g)
646 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); 645 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
647 } 646 }
648 } 647 }
649#else
650 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
651 gk20a_dbg_info("running ASIM with PRIV security disabled");
652 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
653 } else {
654 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
655 if (!val) {
656 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
657 } else {
658 gk20a_dbg_info("priv security is not supported but enabled");
659 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
660 return -EPERM;
661 }
662 }
663#endif
664 648
665 /* priv security dependent ops */ 649 /* priv security dependent ops */
666 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { 650 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {