3 files changed, 38 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index fc98b5ca..c74b9fec 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -1,7 +1,7 @@
 /*
  * GM20B GPC MMU
  *
- * Copyright (c) 2011-2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -262,6 +262,20 @@ static void gr_gm20b_commit_global_pagepool(struct gk20a *g,
 
 }
 
+void gr_gm20b_set_rd_coalesce(struct gk20a *g, u32 data)
+{
+        u32 val;
+
+        gk20a_dbg_fn("");
+
+        val = gk20a_readl(g, gr_gpcs_tpcs_tex_m_dbg2_r());
+        val = set_field(val, gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(),
+                             gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(data));
+        gk20a_writel(g, gr_gpcs_tpcs_tex_m_dbg2_r(), val);
+
+        gk20a_dbg_fn("done");
+}
+
 static int gr_gm20b_handle_sw_method(struct gk20a *g, u32 addr,
                                           u32 class_num, u32 offset, u32 data)
 {
@@ -272,6 +286,9 @@ static int gr_gm20b_handle_sw_method(struct gk20a *g, u32 addr,
                 case NVB1C0_SET_SHADER_EXCEPTIONS:
                         gk20a_gr_set_shader_exceptions(g, data);
                         break;
+                case NVB1C0_SET_RD_COALESCE:
+                        gr_gm20b_set_rd_coalesce(g, data);
+                        break;
                 default:
                         goto fail;
                 }
@@ -288,6 +305,9 @@ static int gr_gm20b_handle_sw_method(struct gk20a *g, u32 addr,
                 case NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE:
                         g->ops.gr.set_alpha_circular_buffer_size(g, data);
                         break;
+                case NVB197_SET_RD_COALESCE:
+                        gr_gm20b_set_rd_coalesce(g, data);
+                        break;
                 default:
                         goto fail;
                 }
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
index a1aef80b..b94259c5 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
@@ -1,7 +1,7 @@
 /*
  * GM20B GPC MMU
  *
- * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -39,7 +39,9 @@ enum {
 #define NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE   0x02dc
 #define NVB197_SET_CIRCULAR_BUFFER_SIZE         0x1280
 #define NVB197_SET_SHADER_EXCEPTIONS            0x1528
+#define NVB197_SET_RD_COALESCE                  0x102c
 #define NVB1C0_SET_SHADER_EXCEPTIONS            0x1528
+#define NVB1C0_SET_RD_COALESCE                  0x0228
 
 #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0
 void gm20b_init_gr(struct gpu_ops *gops);
@@ -48,5 +50,6 @@ void gr_gm20b_commit_global_attrib_cb(struct gk20a *g,
                                       u64 addr, bool patch);
 int gr_gm20b_init_fs_state(struct gk20a *g);
 int gm20b_gr_tpc_disable_override(struct gk20a *g, u32 mask);
+void gr_gm20b_set_rd_coalesce(struct gk20a *g, u32 data);
 
 #endif
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
index 68b5a6d4..9f7fea45 100644
--- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -2254,6 +2254,18 @@ static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void)
 {
         return 0x005030f8;
 }
+static inline u32 gr_gpcs_tpcs_tex_m_dbg2_r(void)
+{
+        return 0x00419a3c;
+}
+static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(u32 v)
+{
+        return (v & 0x1) << 2;
+}
+static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(void)
+{
+        return 0x1 << 2;
+}
 static inline u32 gr_gpccs_falcon_addr_r(void)
 {
         return 0x0041a0ac;