diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 23 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 4 |
3 files changed, 28 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index c67f7870..d00181af 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B GPC MMU | 2 | * GM20B GPC MMU |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -33,6 +33,7 @@ | |||
33 | #include <nvgpu/channel.h> | 33 | #include <nvgpu/channel.h> |
34 | 34 | ||
35 | #include "gk20a/gr_gk20a.h" | 35 | #include "gk20a/gr_gk20a.h" |
36 | #include "gk20a/regops_gk20a.h" | ||
36 | 37 | ||
37 | #include "gr_gm20b.h" | 38 | #include "gr_gm20b.h" |
38 | #include "pmu_gm20b.h" | 39 | #include "pmu_gm20b.h" |
@@ -1455,6 +1456,26 @@ u32 gr_gm20b_get_pmm_per_chiplet_offset(void) | |||
1455 | return (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + 1); | 1456 | return (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + 1); |
1456 | } | 1457 | } |
1457 | 1458 | ||
1459 | int gm20b_gr_set_mmu_debug_mode(struct gk20a *g, | ||
1460 | struct channel_gk20a *ch, bool enable) | ||
1461 | { | ||
1462 | struct nvgpu_dbg_reg_op ctx_ops = { | ||
1463 | .op = REGOP(WRITE_32), | ||
1464 | .type = REGOP(TYPE_GR_CTX), | ||
1465 | .offset = gr_gpcs_pri_mmu_debug_ctrl_r(), | ||
1466 | .value_lo = enable ? | ||
1467 | gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f() : | ||
1468 | gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f(), | ||
1469 | }; | ||
1470 | int err; | ||
1471 | |||
1472 | err = gr_gk20a_exec_ctx_ops(ch, &ctx_ops, 1, 1, 0, NULL); | ||
1473 | if (err != 0) { | ||
1474 | nvgpu_err(g, "Failed to access register"); | ||
1475 | } | ||
1476 | return err; | ||
1477 | } | ||
1478 | |||
1458 | void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable) | 1479 | void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable) |
1459 | { | 1480 | { |
1460 | u32 reg_val, gpc_debug_ctrl; | 1481 | u32 reg_val, gpc_debug_ctrl; |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index 084b6157..81916c05 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B GPC MMU | 2 | * GM20B GPC MMU |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -125,5 +125,7 @@ int gr_gm20b_get_preemption_mode_flags(struct gk20a *g, | |||
125 | void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | 125 | void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, |
126 | u32 global_esr); | 126 | u32 global_esr); |
127 | u32 gr_gm20b_get_pmm_per_chiplet_offset(void); | 127 | u32 gr_gm20b_get_pmm_per_chiplet_offset(void); |
128 | int gm20b_gr_set_mmu_debug_mode(struct gk20a *g, | ||
129 | struct channel_gk20a *ch, bool enable); | ||
128 | void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable); | 130 | void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable); |
129 | #endif /* NVGPU_GM20B_GR_GM20B_H */ | 131 | #endif /* NVGPU_GM20B_GR_GM20B_H */ |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index c978f9aa..0865ace4 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B Graphics | 2 | * GM20B Graphics |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -277,6 +277,7 @@ static const struct gpu_ops gm20b_ops = { | |||
277 | .get_lrf_tex_ltc_dram_override = NULL, | 277 | .get_lrf_tex_ltc_dram_override = NULL, |
278 | .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, | 278 | .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, |
279 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, | 279 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, |
280 | .set_mmu_debug_mode = gm20b_gr_set_mmu_debug_mode, | ||
280 | .record_sm_error_state = gm20b_gr_record_sm_error_state, | 281 | .record_sm_error_state = gm20b_gr_record_sm_error_state, |
281 | .clear_sm_error_state = gm20b_gr_clear_sm_error_state, | 282 | .clear_sm_error_state = gm20b_gr_clear_sm_error_state, |
282 | .suspend_contexts = gr_gk20a_suspend_contexts, | 283 | .suspend_contexts = gr_gk20a_suspend_contexts, |
@@ -753,6 +754,7 @@ int gm20b_init_hal(struct gk20a *g) | |||
753 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | 754 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); |
754 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | 755 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); |
755 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false); | 756 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false); |
757 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, false); | ||
756 | 758 | ||
757 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ | 759 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ |
758 | if (gops->fuse.check_priv_security(g)) { | 760 | if (gops->fuse.check_priv_security(g)) { |