3 files changed, 28 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index c67f7870..d00181af 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -1,7 +1,7 @@
 /*
  * GM20B GPC MMU
  *
- * Copyright (c) 2011-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -33,6 +33,7 @@
 #include <nvgpu/channel.h>
 
 #include "gk20a/gr_gk20a.h"
+#include "gk20a/regops_gk20a.h"
 
 #include "gr_gm20b.h"
 #include "pmu_gm20b.h"
@@ -1455,6 +1456,26 @@ u32 gr_gm20b_get_pmm_per_chiplet_offset(void)
         return (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + 1);
 }
 
+int gm20b_gr_set_mmu_debug_mode(struct gk20a *g,
+                struct channel_gk20a *ch, bool enable)
+{
+        struct nvgpu_dbg_reg_op ctx_ops = {
+                .op = REGOP(WRITE_32),
+                .type = REGOP(TYPE_GR_CTX),
+                .offset = gr_gpcs_pri_mmu_debug_ctrl_r(),
+                .value_lo = enable ?
+                        gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f() :
+                        gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f(),
+        };
+        int err;
+
+        err = gr_gk20a_exec_ctx_ops(ch, &ctx_ops, 1, 1, 0, NULL);
+        if (err != 0) {
+                nvgpu_err(g, "Failed to access register");
+        }
+        return err;
+}
+
 void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable)
 {
         u32 reg_val, gpc_debug_ctrl;
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
index 084b6157..81916c05 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
@@ -1,7 +1,7 @@
 /*
  * GM20B GPC MMU
  *
- * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -125,5 +125,7 @@ int gr_gm20b_get_preemption_mode_flags(struct gk20a *g,
 void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
                         u32 global_esr);
 u32 gr_gm20b_get_pmm_per_chiplet_offset(void);
+int gm20b_gr_set_mmu_debug_mode(struct gk20a *g,
+                struct channel_gk20a *ch, bool enable);
 void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable);
 #endif /* NVGPU_GM20B_GR_GM20B_H */
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index c978f9aa..0865ace4 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -1,7 +1,7 @@
 /*
  * GM20B Graphics
  *
- * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -277,6 +277,7 @@ static const struct gpu_ops gm20b_ops = {
                 .get_lrf_tex_ltc_dram_override = NULL,
                 .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode,
                 .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode,
+                .set_mmu_debug_mode = gm20b_gr_set_mmu_debug_mode,
                 .record_sm_error_state = gm20b_gr_record_sm_error_state,
                 .clear_sm_error_state = gm20b_gr_clear_sm_error_state,
                 .suspend_contexts = gr_gk20a_suspend_contexts,
@@ -753,6 +754,7 @@ int gm20b_init_hal(struct gk20a *g)
         __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
         __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
         __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false);
+        __nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, false);
 
         /* Read fuses to check if gpu needs to boot in secure/non-secure mode */
         if (gops->fuse.check_priv_security(g)) {