diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.h | 6 |
5 files changed, 24 insertions, 17 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 5d9cc32c..f60d880d 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -42,7 +42,7 @@ static void gr_gm20b_init_gpc_mmu(struct gk20a *g) | |||
42 | 42 | ||
43 | gk20a_dbg_info("initialize gpc mmu"); | 43 | gk20a_dbg_info("initialize gpc mmu"); |
44 | 44 | ||
45 | if (!g->ops.privsecurity) { | 45 | if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { |
46 | /* Bypass MMU check for non-secure boot. For | 46 | /* Bypass MMU check for non-secure boot. For |
47 | * secure-boot,this register write has no-effect */ | 47 | * secure-boot,this register write has no-effect */ |
48 | gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffff); | 48 | gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffff); |
@@ -680,7 +680,7 @@ static int gr_gm20b_load_ctxsw_ucode_segments(struct gk20a *g, u64 addr_base, | |||
680 | gr_gk20a_load_ctxsw_ucode_boot(g, addr_base, segments, reg_offset); | 680 | gr_gk20a_load_ctxsw_ucode_boot(g, addr_base, segments, reg_offset); |
681 | 681 | ||
682 | /* start the falcon immediately if PRIV security is disabled*/ | 682 | /* start the falcon immediately if PRIV security is disabled*/ |
683 | if (!g->ops.privsecurity) { | 683 | if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { |
684 | gk20a_writel(g, reg_offset + gr_fecs_cpuctl_r(), | 684 | gk20a_writel(g, reg_offset + gr_fecs_cpuctl_r(), |
685 | gr_fecs_cpuctl_startcpu_f(0x01)); | 685 | gr_fecs_cpuctl_startcpu_f(0x01)); |
686 | } | 686 | } |
@@ -1542,8 +1542,10 @@ static void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | |||
1542 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset, 0); | 1542 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset, 0); |
1543 | } | 1543 | } |
1544 | 1544 | ||
1545 | void gm20b_init_gr(struct gpu_ops *gops) | 1545 | void gm20b_init_gr(struct gk20a *g) |
1546 | { | 1546 | { |
1547 | struct gpu_ops *gops = &g->ops; | ||
1548 | |||
1547 | gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu; | 1549 | gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu; |
1548 | gops->gr.bundle_cb_defaults = gr_gm20b_bundle_cb_defaults; | 1550 | gops->gr.bundle_cb_defaults = gr_gm20b_bundle_cb_defaults; |
1549 | gops->gr.cb_size_default = gr_gm20b_cb_size_default; | 1551 | gops->gr.cb_size_default = gr_gm20b_cb_size_default; |
@@ -1565,7 +1567,7 @@ void gm20b_init_gr(struct gpu_ops *gops) | |||
1565 | gops->gr.init_fs_state = gr_gm20b_init_fs_state; | 1567 | gops->gr.init_fs_state = gr_gm20b_init_fs_state; |
1566 | gops->gr.set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask; | 1568 | gops->gr.set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask; |
1567 | gops->gr.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments; | 1569 | gops->gr.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments; |
1568 | if (gops->privsecurity) | 1570 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) |
1569 | gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; | 1571 | gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; |
1570 | else | 1572 | else |
1571 | gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; | 1573 | gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index e7dd091a..d3adacd8 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h | |||
@@ -36,7 +36,7 @@ enum { | |||
36 | #define NVB1C0_SET_RD_COALESCE 0x0228 | 36 | #define NVB1C0_SET_RD_COALESCE 0x0228 |
37 | 37 | ||
38 | #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 | 38 | #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 |
39 | void gm20b_init_gr(struct gpu_ops *gops); | 39 | void gm20b_init_gr(struct gk20a *g); |
40 | void gr_gm20b_commit_global_attrib_cb(struct gk20a *g, | 40 | void gr_gm20b_commit_global_attrib_cb(struct gk20a *g, |
41 | struct channel_ctx_gk20a *ch_ctx, | 41 | struct channel_ctx_gk20a *ch_ctx, |
42 | u64 addr, bool patch); | 42 | u64 addr, bool patch); |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 01e277ce..228e1a97 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -356,38 +356,38 @@ int gm20b_init_hal(struct gk20a *g) | |||
356 | 356 | ||
357 | #ifdef CONFIG_TEGRA_ACR | 357 | #ifdef CONFIG_TEGRA_ACR |
358 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | 358 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { |
359 | gops->privsecurity = 1; | 359 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); |
360 | } else { | 360 | } else { |
361 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | 361 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); |
362 | if (!val) { | 362 | if (!val) { |
363 | gk20a_dbg_info("priv security is disabled in HW"); | 363 | gk20a_dbg_info("priv security is disabled in HW"); |
364 | gops->privsecurity = 0; | 364 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); |
365 | } else { | 365 | } else { |
366 | gops->privsecurity = 1; | 366 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); |
367 | } | 367 | } |
368 | } | 368 | } |
369 | #else | 369 | #else |
370 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | 370 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { |
371 | gk20a_dbg_info("running ASIM with PRIV security disabled"); | 371 | gk20a_dbg_info("running ASIM with PRIV security disabled"); |
372 | gops->privsecurity = 0; | 372 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); |
373 | } else { | 373 | } else { |
374 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | 374 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); |
375 | if (!val) { | 375 | if (!val) { |
376 | gops->privsecurity = 0; | 376 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); |
377 | } else { | 377 | } else { |
378 | gk20a_dbg_info("priv security is not supported but enabled"); | 378 | gk20a_dbg_info("priv security is not supported but enabled"); |
379 | gops->privsecurity = 1; | 379 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); |
380 | return -EPERM; | 380 | return -EPERM; |
381 | } | 381 | } |
382 | } | 382 | } |
383 | #endif | 383 | #endif |
384 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; | 384 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; |
385 | gm20b_init_gr(gops); | 385 | gm20b_init_gr(g); |
386 | gm20b_init_fb(gops); | 386 | gm20b_init_fb(gops); |
387 | gm20b_init_ce2(gops); | 387 | gm20b_init_ce2(gops); |
388 | gm20b_init_gr_ctx(gops); | 388 | gm20b_init_gr_ctx(gops); |
389 | gm20b_init_mm(gops); | 389 | gm20b_init_mm(gops); |
390 | gm20b_init_pmu_ops(gops); | 390 | gm20b_init_pmu_ops(g); |
391 | gm20b_init_clk_ops(gops); | 391 | gm20b_init_clk_ops(gops); |
392 | gm20b_init_regops(gops); | 392 | gm20b_init_regops(gops); |
393 | gm20b_init_therm_ops(gops); | 393 | gm20b_init_therm_ops(gops); |
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 0f99c67e..98cd3906 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
@@ -16,6 +16,7 @@ | |||
16 | #include <nvgpu/timers.h> | 16 | #include <nvgpu/timers.h> |
17 | #include <nvgpu/pmu.h> | 17 | #include <nvgpu/pmu.h> |
18 | #include <nvgpu/fuse.h> | 18 | #include <nvgpu/fuse.h> |
19 | #include <nvgpu/enabled.h> | ||
19 | 20 | ||
20 | #include "gk20a/gk20a.h" | 21 | #include "gk20a/gk20a.h" |
21 | #include "gk20a/pmu_gk20a.h" | 22 | #include "gk20a/pmu_gk20a.h" |
@@ -273,9 +274,11 @@ static void pmu_dump_security_fuses_gm20b(struct gk20a *g) | |||
273 | val); | 274 | val); |
274 | } | 275 | } |
275 | 276 | ||
276 | void gm20b_init_pmu_ops(struct gpu_ops *gops) | 277 | void gm20b_init_pmu_ops(struct gk20a *g) |
277 | { | 278 | { |
278 | if (gops->privsecurity) { | 279 | struct gpu_ops *gops = &g->ops; |
280 | |||
281 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { | ||
279 | gm20b_init_secure_pmu(gops); | 282 | gm20b_init_secure_pmu(gops); |
280 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; | 283 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; |
281 | gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode; | 284 | gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode; |
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h index e3deb6ef..424fab35 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B PMU | 2 | * GM20B PMU |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -16,7 +16,9 @@ | |||
16 | #ifndef __PMU_GM20B_H_ | 16 | #ifndef __PMU_GM20B_H_ |
17 | #define __PMU_GM20B_H_ | 17 | #define __PMU_GM20B_H_ |
18 | 18 | ||
19 | void gm20b_init_pmu_ops(struct gpu_ops *gops); | 19 | struct gk20a; |
20 | |||
21 | void gm20b_init_pmu_ops(struct gk20a *g); | ||
20 | void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags); | 22 | void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags); |
21 | int gm20b_pmu_init_acr(struct gk20a *g); | 23 | int gm20b_pmu_init_acr(struct gk20a *g); |
22 | void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr); | 24 | void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr); |