4 files changed, 73 insertions, 71 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
index 2d932b67..bcad4437 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
@@ -397,7 +397,7 @@ int prepare_ucode_blob(struct gk20a *g)
         plsfm = &lsfm_l;
         memset((void *)plsfm, 0, sizeof(struct ls_flcn_mgr));
         gm20b_dbg_pmu("fetching GMMU regs\n");
-        gm20b_mm_mmu_vpr_info_fetch(g);
+        g->ops.fb.vpr_info_fetch(g);
         gr_gk20a_init_ctxsw_ucode(g);
 
         g->ops.pmu.get_wpr(g, &wpr_inf);
diff --git a/drivers/gpu/nvgpu/gm20b/fb_gm20b.c b/drivers/gpu/nvgpu/gm20b/fb_gm20b.c
index 985248b0..b50cb2d1 100644
--- a/drivers/gpu/nvgpu/gm20b/fb_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/fb_gm20b.c
@@ -22,6 +22,9 @@
 #include <nvgpu/hw/gm20b/hw_fb_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_top_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_gmmu_gm20b.h>
+#include <nvgpu/hw/gm20b/hw_gr_gm20b.h>
+
+#define VPR_INFO_FETCH_WAIT     (5)
 
 static void fb_gm20b_init_fs_state(struct gk20a *g)
 {
@@ -140,15 +143,84 @@ static void gm20b_fb_dump_vpr_wpr_info(struct gk20a *g)
 
 }
 
+static int gm20b_fb_vpr_info_fetch_wait(struct gk20a *g,
+                                            unsigned int msec)
+{
+        struct nvgpu_timeout timeout;
+
+        nvgpu_timeout_init(g, &timeout, msec, NVGPU_TIMER_CPU_TIMER);
+
+        do {
+                u32 val;
+
+                val = gk20a_readl(g, fb_mmu_vpr_info_r());
+                if (fb_mmu_vpr_info_fetch_v(val) ==
+                    fb_mmu_vpr_info_fetch_false_v())
+                        return 0;
+
+        } while (!nvgpu_timeout_expired(&timeout));
+
+        return -ETIMEDOUT;
+}
+
+int gm20b_fb_vpr_info_fetch(struct gk20a *g)
+{
+        if (gm20b_fb_vpr_info_fetch_wait(g, VPR_INFO_FETCH_WAIT)) {
+                return -ETIME;
+        }
+
+        gk20a_writel(g, fb_mmu_vpr_info_r(),
+                        fb_mmu_vpr_info_fetch_true_v());
+
+        return gm20b_fb_vpr_info_fetch_wait(g, VPR_INFO_FETCH_WAIT);
+}
+
+static bool gm20b_fb_debug_mode_enabled(struct gk20a *g)
+{
+        u32 debug_ctrl = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r());
+        return gr_gpcs_pri_mmu_debug_ctrl_debug_v(debug_ctrl) ==
+                gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v();
+}
+
+static void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable)
+{
+        u32 reg_val, fb_debug_ctrl, gpc_debug_ctrl;
+
+        if (enable) {
+                fb_debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_f();
+                gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f();
+                g->mmu_debug_ctrl = true;
+        } else {
+                fb_debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_f();
+                gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f();
+                g->mmu_debug_ctrl = false;
+        }
+
+        reg_val = gk20a_readl(g, fb_mmu_debug_ctrl_r());
+        reg_val = set_field(reg_val,
+                        fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl);
+        gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val);
+
+        reg_val = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r());
+        reg_val = set_field(reg_val,
+                        gr_gpcs_pri_mmu_debug_ctrl_debug_m(), gpc_debug_ctrl);
+        gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), reg_val);
+}
+
 void gm20b_init_fb(struct gpu_ops *gops)
 {
         gops->fb.reset = fb_gk20a_reset;
+        gops->fb.init_hw = gk20a_fb_init_hw;
         gops->fb.init_fs_state = fb_gm20b_init_fs_state;
         gops->fb.set_mmu_page_size = gm20b_fb_set_mmu_page_size;
         gops->fb.set_use_full_comp_tag_line = gm20b_fb_set_use_full_comp_tag_line;
         gops->fb.compression_page_size = gm20b_fb_compression_page_size;
         gops->fb.compressible_page_size = gm20b_fb_compressible_page_size;
+        gops->fb.vpr_info_fetch = gm20b_fb_vpr_info_fetch;
         gops->fb.dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info;
+        gops->fb.is_debug_mode_enabled = gm20b_fb_debug_mode_enabled;
+        gops->fb.set_debug_mode = gm20b_fb_set_debug_mode;
+        gops->fb.tlb_invalidate = gk20a_fb_tlb_invalidate;
         gm20b_init_uncompressed_kind_map();
         gm20b_init_kind_attr();
 }
diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
index cd1a106d..0b3192cc 100644
--- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
@@ -22,75 +22,9 @@
 #include <nvgpu/timers.h>
 
 #include <nvgpu/hw/gm20b/hw_gmmu_gm20b.h>
-#include <nvgpu/hw/gm20b/hw_fb_gm20b.h>
-#include <nvgpu/hw/gm20b/hw_gr_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_ram_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_bus_gm20b.h>
 
-static int gm20b_mm_mmu_vpr_info_fetch_wait(struct gk20a *g,
-                                            unsigned int msec)
-{
-        struct nvgpu_timeout timeout;
-
-        nvgpu_timeout_init(g, &timeout, msec, NVGPU_TIMER_CPU_TIMER);
-
-        do {
-                u32 val;
-
-                val = gk20a_readl(g, fb_mmu_vpr_info_r());
-                if (fb_mmu_vpr_info_fetch_v(val) ==
-                    fb_mmu_vpr_info_fetch_false_v())
-                        return 0;
-
-        } while (!nvgpu_timeout_expired(&timeout));
-
-        return -ETIMEDOUT;
-}
-
-int gm20b_mm_mmu_vpr_info_fetch(struct gk20a *g)
-{
-        if (gm20b_mm_mmu_vpr_info_fetch_wait(g, VPR_INFO_FETCH_WAIT)) {
-                return -ETIME;
-        }
-
-        gk20a_writel(g, fb_mmu_vpr_info_r(),
-                        fb_mmu_vpr_info_fetch_true_v());
-
-        return gm20b_mm_mmu_vpr_info_fetch_wait(g, VPR_INFO_FETCH_WAIT);
-}
-
-static bool gm20b_mm_mmu_debug_mode_enabled(struct gk20a *g)
-{
-        u32 debug_ctrl = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r());
-        return gr_gpcs_pri_mmu_debug_ctrl_debug_v(debug_ctrl) ==
-                gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v();
-}
-
-static void gm20b_mm_mmu_set_debug_mode(struct gk20a *g, bool enable)
-{
-        u32 reg_val, fb_debug_ctrl, gpc_debug_ctrl;
-
-        if (enable) {
-                fb_debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_f();
-                gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f();
-                g->mmu_debug_ctrl = true;
-        } else {
-                fb_debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_f();
-                gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f();
-                g->mmu_debug_ctrl = false;
-        }
-
-        reg_val = gk20a_readl(g, fb_mmu_debug_ctrl_r());
-        reg_val = set_field(reg_val,
-                        fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl);
-        gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val);
-
-        reg_val = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r());
-        reg_val = set_field(reg_val,
-                        gr_gpcs_pri_mmu_debug_ctrl_debug_m(), gpc_debug_ctrl);
-        gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), reg_val);
-}
-
 static void gm20b_mm_set_big_page_size(struct gk20a *g,
                                 struct mem_desc *mem, int size)
 {
@@ -157,8 +91,6 @@ static bool gm20b_mm_is_bar1_supported(struct gk20a *g)
 void gm20b_init_mm(struct gpu_ops *gops)
 {
         gops->mm.support_sparse = gm20b_mm_support_sparse;
-        gops->mm.is_debug_mode_enabled = gm20b_mm_mmu_debug_mode_enabled;
-        gops->mm.set_debug_mode = gm20b_mm_mmu_set_debug_mode;
         gops->mm.gmmu_map = gk20a_locked_gmmu_map;
         gops->mm.gmmu_unmap = gk20a_locked_gmmu_unmap;
         gops->mm.vm_remove = gk20a_vm_remove_support;
@@ -168,7 +100,6 @@ void gm20b_init_mm(struct gpu_ops *gops)
         gops->mm.l2_invalidate = gk20a_mm_l2_invalidate;
         gops->mm.l2_flush = gk20a_mm_l2_flush;
         gops->mm.cbc_clean = gk20a_mm_cbc_clean;
-        gops->mm.tlb_invalidate = gk20a_mm_tlb_invalidate;
         gops->mm.set_big_page_size = gm20b_mm_set_big_page_size;
         gops->mm.get_big_page_sizes = gm20b_mm_get_big_page_sizes;
         gops->mm.get_iova_addr = gk20a_mm_iova_addr;
diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.h b/drivers/gpu/nvgpu/gm20b/mm_gm20b.h
index 6939fc1a..99d6c161 100644
--- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.h
@@ -19,7 +19,6 @@ struct gk20a;
 
 #define PDE_ADDR_START(x, y)    ((x) &  ~((0x1UL << (y)) - 1))
 #define PDE_ADDR_END(x, y)      ((x) | ((0x1UL << (y)) - 1))
-#define VPR_INFO_FETCH_WAIT     (5)
 
 void gm20b_init_mm(struct gpu_ops *gops);
 int gm20b_mm_mmu_vpr_info_fetch(struct gk20a *g);