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Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r--drivers/gpu/nvgpu/gm20b/gr_gm20b.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 4c49f734..c692d975 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -1339,7 +1339,7 @@ int gm20b_gr_update_sm_error_state(struct gk20a *g,
1339 gk20a_writel(g, gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r() + offset, 1339 gk20a_writel(g, gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r() + offset,
1340 gr->sm_error_states[sm_id].hww_warp_esr_report_mask); 1340 gr->sm_error_states[sm_id].hww_warp_esr_report_mask);
1341 } else { 1341 } else {
1342 err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); 1342 err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx, false);
1343 if (err) 1343 if (err)
1344 goto enable_ctxsw; 1344 goto enable_ctxsw;
1345 1345
@@ -1352,7 +1352,7 @@ int gm20b_gr_update_sm_error_state(struct gk20a *g,
1352 gr->sm_error_states[sm_id].hww_warp_esr_report_mask, 1352 gr->sm_error_states[sm_id].hww_warp_esr_report_mask,
1353 true); 1353 true);
1354 1354
1355 gr_gk20a_ctx_patch_write_end(g, ch_ctx); 1355 gr_gk20a_ctx_patch_write_end(g, ch_ctx, false);
1356 } 1356 }
1357 1357
1358enable_ctxsw: 1358enable_ctxsw: